From: Mateusz Polchlopek <mateusz.polchlo...@intel.com>
Date: Tue, 30 Jul 2024 05:14:58 -0400
> From: Jacob Keller <jacob.e.kel...@intel.com>
>
> Support for allowing VF to negotiate the descriptor format requires that
> the VF specify which descriptor format to use when requesting Rx queues.
> The VF is supposed to request the set of supported formats via the new
> VIRTCHNL_OP_GET_SUPPORTED_RXDIDS, and then set one of the supported
> formats in the rxdid field of the virtchnl_rxq_info structure.
[...]
> +/* RX descriptor ID bitmasks */
> +enum virtchnl_rx_desc_id_bitmasks {
> + VIRTCHNL_RXDID_0_16B_BASE_M =
> BIT(VIRTCHNL_RXDID_0_16B_BASE),
> + VIRTCHNL_RXDID_1_32B_BASE_M =
> BIT(VIRTCHNL_RXDID_1_32B_BASE),
> + VIRTCHNL_RXDID_2_FLEX_SQ_NIC_M =
> BIT(VIRTCHNL_RXDID_2_FLEX_SQ_NIC),
> + VIRTCHNL_RXDID_3_FLEX_SQ_SW_M =
> BIT(VIRTCHNL_RXDID_3_FLEX_SQ_SW),
Macro compression? ^.^
#define VIRTCHNL_RXDID_BIT(x) BIT(VIRTCHNL_RXDID_##x)
VIRTCHNL_RXDID_0_16B_BASE_M =
VIRTCHNL_RXDID_BIT(0_16B_BASE),
and so on...
(optionally)
> + VIRTCHNL_RXDID_4_FLEX_SQ_NIC_VEB_M =
> BIT(VIRTCHNL_RXDID_4_FLEX_SQ_NIC_VEB),
> + VIRTCHNL_RXDID_5_FLEX_SQ_NIC_ACL_M =
> BIT(VIRTCHNL_RXDID_5_FLEX_SQ_NIC_ACL),
> + VIRTCHNL_RXDID_6_FLEX_SQ_NIC_2_M =
> BIT(VIRTCHNL_RXDID_6_FLEX_SQ_NIC_2),
> + VIRTCHNL_RXDID_7_HW_RSVD_M = BIT(VIRTCHNL_RXDID_7_HW_RSVD),
> + /* 8 through 15 are reserved */
> + VIRTCHNL_RXDID_16_COMMS_GENERIC_M =
> BIT(VIRTCHNL_RXDID_16_COMMS_GENERIC),
> + VIRTCHNL_RXDID_17_COMMS_AUX_VLAN_M =
> BIT(VIRTCHNL_RXDID_17_COMMS_AUX_VLAN),
> + VIRTCHNL_RXDID_18_COMMS_AUX_IPV4_M =
> BIT(VIRTCHNL_RXDID_18_COMMS_AUX_IPV4),
> + VIRTCHNL_RXDID_19_COMMS_AUX_IPV6_M =
> BIT(VIRTCHNL_RXDID_19_COMMS_AUX_IPV6),
> + VIRTCHNL_RXDID_20_COMMS_AUX_FLOW_M =
> BIT(VIRTCHNL_RXDID_20_COMMS_AUX_FLOW),
> + VIRTCHNL_RXDID_21_COMMS_AUX_TCP_M =
> BIT(VIRTCHNL_RXDID_21_COMMS_AUX_TCP),
> + /* 22 through 63 are reserved */
> +};
> +
> /* virtchnl_rxq_info_flags
> *
> * Definition of bits in the flags field of the virtchnl_rxq_info structure.
> @@ -338,6 +378,11 @@ struct virtchnl_rxq_info {
> u32 databuffer_size;
> u32 max_pkt_size;
> u8 crc_disable;
> + /* see enum virtchnl_rx_desc_ids;
> + * only used when VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC is supported. Note
> + * that when the offload is not supported, the descriptor format aligns
> + * with VIRTCHNL_RXDID_1_32B_BASE.
> + */
> u8 rxdid;
Same as in the previous patch, this can be enum:8.
> u8 flags; /* see virtchnl_rxq_info_flags */
> u8 pad1;
> @@ -1041,6 +1086,7 @@ struct virtchnl_filter {
> VIRTCHNL_CHECK_STRUCT_LEN(272, virtchnl_filter);
>
> struct virtchnl_supported_rxdids {
> + /* see enum virtchnl_rx_desc_id_bitmasks */
> u64 supported_rxdids;
If this is u64, then virtchnl_rx_desc_id_bitmasks should use BIT_ULL(),
not BIT().
> };
Thanks,
Olek
