From: Karol Kolacinski <karol.kolacin...@intel.com>
Date: Thu, 4 Apr 2024 11:09:51 +0200
> From: Sergey Temerkhanov <sergey.temerkha...@intel.com>
>
> Introduce functions enabling/disabling Tx TS interrupts
> for the E822 and ETH56G PHYs
>
> Signed-off-by: Sergey Temerkhanov <sergey.temerkha...@intel.com>
> Reviewed-by: Przemek Kitszel <przemyslaw.kits...@intel.com>
> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalew...@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacin...@intel.com>
[...]
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> index 0d8e051ff93b..6d92b5d6b4d9 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c
> @@ -2715,6 +2715,37 @@ ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8
> quad, u64 *tstamp_ready)
> return 0;
> }
>
> +/**
> + * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt
> + * @hw: pointer to the HW struct
> + * @quad: the timestamp quad
> + * @ena: enable or disable interrupt
> + * @threshold: interrupt threshold
> + *
> + * Configure TX timestamp interrupt for the specified quad
> + */
> +
> +int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold)
> +{
> + int err;
> + u32 val;
> +
> + err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val);
> + if (err)
> + return err;
> +
> + val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
> + if (ena) {
> + val |= Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M;
> + val &= ~Q_REG_TX_MEM_GBL_CFG_INTR_THR_M;
> + val |= FIELD_PREP(Q_REG_TX_MEM_GBL_CFG_INTR_THR_M, threshold);
> + }
> +
> + err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val);
> +
> + return err;
return ice_write_quad_reg_e82x(...
> +}
> +
> /**
> * ice_ptp_init_phy_e82x - initialize PHY parameters
> * @ptp: pointer to the PTP HW struct
> diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
> b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
> index 6246de3bacf3..5645b20a9f87 100644
> --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
> +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.h
> @@ -265,6 +265,7 @@ int ice_stop_phy_timer_e82x(struct ice_hw *hw, u8 port,
> bool soft_reset);
> int ice_start_phy_timer_e82x(struct ice_hw *hw, u8 port);
> int ice_phy_cfg_tx_offset_e82x(struct ice_hw *hw, u8 port);
> int ice_phy_cfg_rx_offset_e82x(struct ice_hw *hw, u8 port);
> +int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8
> threshold);
>
> /* E810 family functions */
> int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
> @@ -342,11 +343,8 @@ int ice_cgu_get_output_pin_state_caps(struct ice_hw *hw,
> u8 pin_id,
> #define Q_REG_TX_MEM_GBL_CFG 0xC08
> #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
> #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
> -#define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S 1
> #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
> -#define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S 9
> #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
> -#define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S 15
> #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
>
> /* Tx Timestamp data registers */
Thanks,
Olek
