On Fri Feb 16 2024, Vinicius Costa Gomes wrote:
> Fix "double" clearing of interrupts, which can cause external events
> or timestamps to be missed.
>
> The IGC_TSIRC Time Sync Interrupt Cause register can be cleared in two
> ways, by either reading it or by writing '1' into the specific cause
> bit. This is documented in section 8.16.1.
>
> The following flow was used:
> 1. read IGC_TSIRC into 'tsicr';
> 2. handle the interrupts present in 'tsirc' and mark them in 'ack';
> 3. write 'ack' into IGC_TSICR;
>
> As both (1) and (3) will clear the interrupt cause, if an interrupt
> happens between (1) and (3) it will be ignored, causing events to be
> missed.
>
> Remove the extra clear in (3).
>
> Fixes: 2c344ae24501 ("igc: Add support for TX timestamping")
> Signed-off-by: Vinicius Costa Gomes <vinicius.go...@intel.com>No obvious issues found while testing. Reviewed-by: Kurt Kanzenbach <k...@linutronix.de> Tested-by: Kurt Kanzenbach <k...@linutronix.de> # Intel i225 Thanks!
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