Forcing SMBUS in enable ULP flow causes sporadically PHY loss on
MTL systems. This is a legacy configuration that is no longer
required on newer PHYs.
Therefore we remove it for MTL systems and above.

Fixes: 6607c99e7034 ("e1000e: i219 - fix to enable both ULP and EEE in Sx 
state")
Signed-off-by: Vitaly Lifshits <vitaly.lifsh...@intel.com>
Co-developed-by: Dima Ruinskiy <dima.ruins...@intel.com>
Signed-off-by: Dima Ruinskiy <dima.ruins...@intel.com>
---
 drivers/net/ethernet/intel/e1000e/ich8lan.c | 25 ++++++++++++---------
 1 file changed, 14 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.c 
b/drivers/net/ethernet/intel/e1000e/ich8lan.c
index 39e9fc601bf5..816195e2f2f9 100644
--- a/drivers/net/ethernet/intel/e1000e/ich8lan.c
+++ b/drivers/net/ethernet/intel/e1000e/ich8lan.c
@@ -1147,18 +1147,21 @@ s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool 
to_sx)
        ret_val = hw->phy.ops.acquire(hw);
        if (ret_val)
                goto out;
+       /* Forcing SMBUS on MTL and above is not required */
+       if (hw->mac.type < e1000_pch_mtp) {
+               /* Force SMBus mode in PHY */
+               ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL,
+                                                      &phy_reg);
+               if (ret_val)
+                       goto release;
+               phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
+               e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
 
-       /* Force SMBus mode in PHY */
-       ret_val = e1000_read_phy_reg_hv_locked(hw, CV_SMB_CTRL, &phy_reg);
-       if (ret_val)
-               goto release;
-       phy_reg |= CV_SMB_CTRL_FORCE_SMBUS;
-       e1000_write_phy_reg_hv_locked(hw, CV_SMB_CTRL, phy_reg);
-
-       /* Force SMBus mode in MAC */
-       mac_reg = er32(CTRL_EXT);
-       mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
-       ew32(CTRL_EXT, mac_reg);
+               /* Force SMBus mode in MAC */
+               mac_reg = er32(CTRL_EXT);
+               mac_reg |= E1000_CTRL_EXT_FORCE_SMBUS;
+               ew32(CTRL_EXT, mac_reg);
+       }
 
        /* Si workaround for ULP entry flow on i127/rev6 h/w.  Enable
         * LPLU and disable Gig speed when entering ULP
-- 
2.34.1

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