From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
We notice two identical copies of the shadow register table and
following from that removal can also unify CHV and Gen9 write
mmio functions and macros into a single implementation.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 69 +++++++------------------------------
1 file changed, 12 insertions(+), 57 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 4f9f57774e2a..893d73c7368a 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -706,7 +706,7 @@ static const struct intel_forcewake_range __chv_fw_ranges[]
= {
GEN_FW_RANGE(0x30000, 0x37fff, FORCEWAKE_MEDIA),
};
-#define __chv_reg_write_fw_domains(offset) \
+#define __fwtbl_reg_write_fw_domains(offset) \
({ \
enum forcewake_domains __fwd = 0; \
if (NEEDS_FORCE_WAKE((offset)) && !is_gen8_shadowed(offset)) \
@@ -750,34 +750,6 @@ static const struct intel_forcewake_range
__gen9_fw_ranges[] = {
GEN_FW_RANGE(0x30000, 0x3ffff, FORCEWAKE_MEDIA),
};
-static const i915_reg_t gen9_shadowed_regs[] = {
- RING_TAIL(RENDER_RING_BASE),
- RING_TAIL(GEN6_BSD_RING_BASE),
- RING_TAIL(VEBOX_RING_BASE),
- RING_TAIL(BLT_RING_BASE),
- GEN6_RPNSWREQ,
- GEN6_RC_VIDEO_FREQ,
- /* TODO: Other registers are not yet used */
-};
-
-static bool is_gen9_shadowed(u32 offset)
-{
- int i;
- for (i = 0; i < ARRAY_SIZE(gen9_shadowed_regs); i++)
- if (offset == gen9_shadowed_regs[i].reg)
- return true;
-
- return false;
-}
-
-#define __gen9_reg_write_fw_domains(offset) \
-({ \
- enum forcewake_domains __fwd = 0; \
- if (NEEDS_FORCE_WAKE((offset)) && !is_gen9_shadowed(offset)) \
- __fwd = find_fw_domain(dev_priv, offset); \
- __fwd; \
-})
-
static void
ilk_dummy_write(struct drm_i915_private *dev_priv)
{
@@ -1034,37 +1006,21 @@ gen8_write##x(struct drm_i915_private *dev_priv,
i915_reg_t reg, u##x val, bool
GEN6_WRITE_FOOTER; \
}
-#define __chv_write(x) \
-static void \
-chv_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool
trace) { \
- enum forcewake_domains fw_engine; \
- GEN6_WRITE_HEADER; \
- fw_engine = __chv_reg_write_fw_domains(offset); \
- if (fw_engine) \
- __force_wake_auto(dev_priv, fw_engine); \
- __raw_i915_write##x(dev_priv, reg, val); \
- GEN6_WRITE_FOOTER; \
-}
-
-#define __gen9_write(x) \
+#define __fwtbl_write(x) \
static void \
-gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \
- bool trace) { \
+fwtbl_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val,
bool trace) { \
enum forcewake_domains fw_engine; \
GEN6_WRITE_HEADER; \
- fw_engine = __gen9_reg_write_fw_domains(offset); \
+ fw_engine = __fwtbl_reg_write_fw_domains(offset); \
if (fw_engine) \
__force_wake_auto(dev_priv, fw_engine); \
__raw_i915_write##x(dev_priv, reg, val); \
GEN6_WRITE_FOOTER; \
}
-__gen9_write(8)
-__gen9_write(16)
-__gen9_write(32)
-__chv_write(8)
-__chv_write(16)
-__chv_write(32)
+__fwtbl_write(8)
+__fwtbl_write(16)
+__fwtbl_write(32)
__gen8_write(8)
__gen8_write(16)
__gen8_write(32)
@@ -1072,8 +1028,7 @@ __gen6_write(8)
__gen6_write(16)
__gen6_write(32)
-#undef __gen9_write
-#undef __chv_write
+#undef __fwtbl_write
#undef __gen8_write
#undef __gen6_write
#undef GEN6_WRITE_FOOTER
@@ -1284,13 +1239,13 @@ void intel_uncore_init(struct drm_i915_private
*dev_priv)
default:
case 9:
ASSIGN_FW_DOMAINS_TABLE(__gen9_fw_ranges);
- ASSIGN_WRITE_MMIO_VFUNCS(gen9);
+ ASSIGN_WRITE_MMIO_VFUNCS(fwtbl);
ASSIGN_READ_MMIO_VFUNCS(fwtbl);
break;
case 8:
if (IS_CHERRYVIEW(dev_priv)) {
ASSIGN_FW_DOMAINS_TABLE(__chv_fw_ranges);
- ASSIGN_WRITE_MMIO_VFUNCS(chv);
+ ASSIGN_WRITE_MMIO_VFUNCS(fwtbl);
ASSIGN_READ_MMIO_VFUNCS(fwtbl);
} else {
@@ -1819,11 +1774,11 @@ intel_uncore_forcewake_for_write(struct
drm_i915_private *dev_priv,
switch (INTEL_GEN(dev_priv)) {
case 9:
- fw_domains =
__gen9_reg_write_fw_domains(i915_mmio_reg_offset(reg));
+ fw_domains =
__fwtbl_reg_write_fw_domains(i915_mmio_reg_offset(reg));
break;
case 8:
if (IS_CHERRYVIEW(dev_priv))
- fw_domains =
__chv_reg_write_fw_domains(i915_mmio_reg_offset(reg));
+ fw_domains =
__fwtbl_reg_write_fw_domains(i915_mmio_reg_offset(reg));
else
fw_domains =
__gen8_reg_write_fw_domains(i915_mmio_reg_offset(reg));
break;
--
2.7.4
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