On Fri, Sep 02, 2016 at 04:08:27PM +0300, Mika Kahola wrote:
> On Thu, 2016-09-01 at 15:08 -0700, Manasi Navare wrote:
> > While configuring the pipe during modeset, it should loop
> > starting from max clock and max lane count reducing the
> > lane count and clock in each iteration until the requested mode
> > rate is less than or equal to available link BW.
> >
> > Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_dp.c | 9 ++++-----
> > 1 file changed, 4 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index dfdbe65..e094b25 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -1552,11 +1552,10 @@ intel_dp_compute_config(struct intel_encoder
> > *encoder,
> > for (; bpp >= 6*3; bpp -= 2*3) {
> > mode_rate = intel_dp_link_required(adjusted_mode-
> > >crtc_clock,
> > bpp);
> > -
> > - for (clock = min_clock; clock <= max_clock; clock++)
> > {
> > - for (lane_count = min_lane_count;
> > - lane_count <= max_lane_count;
> > - lane_count <<= 1) {
> > + for (clock = max_clock; clock >= max_clock; clock--)
> The clock should be higher than or equal to min_clock.
Thanks for the review. Yes that is a mistake. I will fix this in the loop.
> > {
> > + for (lane_count = max_lane_count;
> > + lane_count >= min_lane_count;
> > + lane_count >>= 1) {
> >
> > link_clock = common_rates[clock];
> > link_avail =
> > intel_dp_max_data_rate(link_clock,
> --
> Mika Kahola - Intel OTC
>
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