Get the PLLs for HSW/BDW using the platform specific function
and add hooks for enabling upfront link training on HSW and BDW.
Signed-off-by: Manasi Navare <manasi.d.nav...@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 2 ++
drivers/gpu/drm/i915/intel_dp.c | 4 +++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index ef63b4b..1d3ab8a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -2410,6 +2410,8 @@ intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int
clock)
}
} else if (IS_SKYLAKE(dev_priv)) {
pll = skl_find_link_pll(dev_priv, clock);
+ } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+ pll = hsw_ddi_dp_get_dpll(encoder, clock);
}
return pll;
}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index fe156fb..a1cea4d 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -5757,8 +5757,10 @@ intel_dp_init_connector(struct intel_digital_port
*intel_dig_port,
/* Initialize upfront link training vfunc for DP */
if (intel_encoder->type != INTEL_OUTPUT_EDP) {
- if (IS_BROXTON(dev) || IS_SKYLAKE(dev))
+ if (IS_BROXTON(dev) || IS_SKYLAKE(dev) ||
+ IS_BROADWELL(dev) || IS_HASWELL(dev))
intel_dp->upfront_link_train =
intel_ddi_upfront_link_train;
+
}
/* eDP only on port B and/or C on vlv/chv */
--
1.9.1
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