On Tue, Aug 09, 2016 at 11:45:10AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> - standard place when adding new features from new platforms
> - possible to see supported features when dumping struct
> definitions
>
> Feedback from V. Syrjala: remove runtime PM support for snb as it breaks
> hotplug support.
I believe it is better a separated patch on top of this re-org. Just in case
it needs to be reverted.
>
> Signed-off-by: Carlos Santa <carlos.sa...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 6 ++----
> drivers/gpu/drm/i915/i915_pci.c | 6 +++++-
> 2 files changed, 7 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6f2f066..0eaf28f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -771,6 +771,7 @@ struct intel_csr {
> func(is_preliminary) sep \
> func(has_fbc) sep \
> func(has_psr) sep \
> + func(has_runtime_pm) sep \
> func(has_pipe_cxsr) sep \
> func(has_hotplug) sep \
> func(cursor_needs_physical) sep \
> @@ -2769,10 +2770,7 @@ struct drm_i915_cmd_table {
> #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
> #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
> #define HAS_PSR(dev) (INTEL_INFO(dev)->has_psr)
> -#define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
> - IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
> - IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
> - IS_KABYLAKE(dev) || IS_BROXTON(dev))
> +#define HAS_RUNTIME_PM(dev) (INTEL_INFO(dev)->has_runtime_pm)
> #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
> #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index bdc2071..9d78836 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -242,6 +242,7 @@ static const struct intel_device_info
> intel_ivybridge_q_info = {
> #define VLV_FEATURES \
> .gen = 7, .num_pipes = 2, \
> .has_psr = 1, \
> + .has_runtime_pm = 1, \
> .need_gfx_hws = 1, .has_hotplug = 1, \
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
> .display_mmio_offset = VLV_DISPLAY_BASE, \
> @@ -258,7 +259,8 @@ static const struct intel_device_info
> intel_valleyview_info = {
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
> .has_ddi = 1, \
> .has_fpga_dbg = 1, \
> - .has_psr = 1
> + .has_psr = 1, \
> + .has_runtime_pm = 1
>
> static const struct intel_device_info intel_haswell_info = {
> HSW_FEATURES,
> @@ -288,6 +290,7 @@ static const struct intel_device_info
> intel_cherryview_info = {
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
> .is_cherryview = 1,
> .has_psr = 1,
> + .has_runtime_pm = 1,
> .display_mmio_offset = VLV_DISPLAY_BASE,
> GEN_CHV_PIPEOFFSETS,
> CURSOR_OFFSETS,
> @@ -316,6 +319,7 @@ static const struct intel_device_info intel_broxton_info
> = {
> .has_ddi = 1,
> .has_fpga_dbg = 1,
> .has_fbc = 1,
> + .has_runtime_pm = 1,
> .has_pooled_eu = 0,
> GEN_DEFAULT_PIPEOFFSETS,
> IVB_CURSOR_OFFSETS,
> --
> 1.9.1
>
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