DC state reset the frame counter that is a read-only register.
So, besides blocking DC state on vblank let's restore the
drm crtc vblank counter to a place we know it is reliable.
Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4efe20c..82d6896 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2759,7 +2759,9 @@ static int gen8_enable_vblank(struct drm_device *dev,
unsigned int pipe)
static void gen9_prepare_vblank(struct drm_device *dev, unsigned int pipe)
{
struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
intel_display_power_get(dev_priv, POWER_DOMAIN_VBLANK);
+ drm_crtc_vblank_sanitize_counter(crtc);
}
static void gen9_unprepare_vblank(struct drm_device *dev, unsigned int pipe)
--
2.4.3
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