Moving all GPU features to the platform definition allows for
- standard placae when adding new features from new platforms
- possible to see supported features when dumping struct
definitions
Signed-off-by: Carlos Santa <carlos.sa...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_pci.c | 10 +++++++++-
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a58765b..8f5b9fd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -780,6 +780,7 @@ struct intel_csr {
func(has_dp_mst) sep \
func(has_aux_irq) sep \
func(has_gmbus_irq) sep \
+ func(has_fw_blc) sep \
func(has_resource_streamer) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
@@ -2848,7 +2849,7 @@ struct drm_i915_cmd_table {
#define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
-#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
+#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->has_fw_blc)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 50569c1..b44d162 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -82,7 +82,8 @@ static const struct intel_device_info intel_i865g_info = {
};
#define GEN3_FEATURES \
- .gen = 3, .num_pipes = 2,\
+ .gen = 3, .num_pipes = 2, \
+ .has_fw_blc = 1, \
.ring_mask = RENDER_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
@@ -122,6 +123,7 @@ static const struct intel_device_info intel_i945gm_info = {
#define GEN4_FEATURES \
.gen = 4, .num_pipes = 2, \
.has_hotplug = 1, \
+ .has_fw_blc = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
@@ -180,6 +182,7 @@ static const struct intel_device_info intel_pineview_info =
{
.need_gfx_hws = 1, .has_hotplug = 1, \
.has_aux_irq = 1, \
.has_gmbus_irq = 1, \
+ .has_fw_blc = 1, \
.ring_mask = RENDER_RING | BSD_RING, \
GEN_DEFAULT_PIPEOFFSETS, \
CURSOR_OFFSETS
@@ -205,6 +208,7 @@ static const struct intel_device_info intel_ironlake_m_info
= {
.has_rc6p = 1, \
.has_aux_irq = 1, \
.has_gmbus_irq = 1, \
+ .has_fw_blc = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -227,6 +231,7 @@ static const struct intel_device_info
intel_sandybridge_m_info = {
.has_rc6 = 1, \
.has_aux_irq = 1, \
.has_gmbus_irq = 1, \
+ .has_fw_blc = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -262,6 +267,7 @@ static const struct intel_device_info
intel_ivybridge_q_info = {
.has_rc6 = 1, \
.has_aux_irq = 1, \
.has_gmbus_irq = 1, \
+ .has_fw_blc = 1, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -342,6 +348,7 @@ static const struct intel_device_info intel_cherryview_info
= {
.has_dp_mst = 1,
.has_aux_irq = 1,
.has_gmbus_irq = 1,
+ .has_fw_blc = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
@@ -383,6 +390,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_rc6 = 1,
.has_aux_irq = 1,
.has_gmbus_irq = 1,
+ .has_fw_blc = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
--
1.9.1
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