On Tue, Jun 07, 2016 at 09:24:27PM +0300, Imre Deak wrote: > There are two problems with the current way of enabling the DDI PHYs > during driver loading/resuming: > Relying on the HWs dynamic power gating may waste some power and part of > the PHY configuration is dependent on the mode specific DDI lane count. > To solve both of these issues split the PHY initialization, moving one > half of it to the power well code the other half to the modeset code, > similarly to the CHV code. > > Kudos to Ville for explaining about the PHY power gating and other > quirks on CHV, it helped a lot to better understand the BXT PHY which is > quite similar. > > This fixes modeset problems for modes with less than 4 lanes. > > Imre Deak (6): > drm/i915/bxt: Wait for PHY1 GRC calibration synchronously > drm/i915: Factor out intel_power_well_get/put > drm/i915/bxt: Move DDI PHY enabling/disabling to the power well code > drm/i915/bxt: Set DDI PHY lane latency optimization during modeset > drm/i915/bxt: Rename broxton to bxt in PHY/CDCLK function prefixes > drm/i915/bxt: Sanitiy check the PHY lane power down status
Series lgtm Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com> > > drivers/gpu/drm/i915/i915_reg.h | 12 ++ > drivers/gpu/drm/i915/intel_ddi.c | 222 > ++++++++++++++++++-------------- > drivers/gpu/drm/i915/intel_display.c | 33 +++-- > drivers/gpu/drm/i915/intel_drv.h | 19 ++- > drivers/gpu/drm/i915/intel_runtime_pm.c | 133 ++++++++++++++++--- > 5 files changed, 291 insertions(+), 128 deletions(-) > > -- > 2.5.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
