On Thu, Jun 09, 2016 at 11:31:20AM +0300, Jani Nikula wrote: > On Thu, 09 Jun 2016, Dhinakaran Pandiyan <dhinakaran.pandi...@intel.com> > wrote: > > IGT vblank tests fail on CHV by timing out on VBIs if PSR is enabled. We > > do not get VBIs as the source timing generation is disabled when PSR is > > active. The first two patches written by Rodrigo add drm hooks. Patch 3 > > deactivates PSR when VBI are needed. > > The first thing to do would be to submit a patch that disables PSR by > default on CHV. We can enable it again if and when these patches land.
I already reverted the "enable by default" patch some time ago. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
