From: Robert Bragg <rob...@sixbynine.org>
The newly added intel_context::global_id is suitable (a globally unique
20 bit ID) for giving to the hardware as a unique context identifier.
Compared to using the pinned address of a logical ring context these IDs
are constant for the lifetime of a context whereas a context could be
repinned at different addresses during its lifetime.
Having a stable ID is useful when we need to buffer information
associated with a context based on this ID so the association can't be
lost. For example the OA unit writes out counter reports to a circular
buffer tagged with this ID and we want to be able to accurately filter
reports for a specific context, ideally without the added complexity of
tracking context re-pinning while the OA buffer may contain reports with
older IDs.
Cc: Sourab Gupta <sourab.gu...@intel.com>
Signed-off-by: Robert Bragg <rob...@sixbynine.org>
---
drivers/gpu/drm/i915/i915_debugfs.c | 4 ++--
drivers/gpu/drm/i915/intel_lrc.c | 28 ++++++++++++++--------------
drivers/gpu/drm/i915/intel_lrc.h | 3 +--
3 files changed, 17 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index 931dc60..c172bf5 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2050,7 +2050,7 @@ static void i915_dump_lrc_obj(struct seq_file *m,
}
seq_printf(m, "CONTEXT: %s %u\n", engine->name,
- intel_execlists_ctx_id(ctx, engine));
+ intel_execlists_ctx_id(ctx));
if (!i915_gem_obj_ggtt_bound(ctx_obj))
seq_puts(m, "\tNot bound in GGTT\n");
@@ -2171,7 +2171,7 @@ static int i915_execlists(struct seq_file *m, void *data)
seq_printf(m, "\t%d requests in queue\n", count);
if (head_req) {
seq_printf(m, "\tHead request id: %u\n",
- intel_execlists_ctx_id(head_req->ctx,
engine));
+ intel_execlists_ctx_id(head_req->ctx));
seq_printf(m, "\tHead request tail: %u\n",
head_req->tail);
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 452ea0d..1425ede 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -307,21 +307,23 @@ logical_ring_init_platform_invariants(struct
intel_engine_cs *engine)
* This is what a descriptor looks like, from LSB to MSB:
* bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
* bits 12-31: LRCA, GTT address of (the HWSP of) this context
- * bits 32-51: ctx ID, a globally unique tag (the LRCA again!)
+ * bits 32-51: ctx ID, a globally unique tag (ctx->global_id)
* bits 52-63: reserved, may encode the engine ID (for GuC)
*/
static void
intel_lr_context_descriptor_update(struct intel_context *ctx,
struct intel_engine_cs *engine)
{
- uint64_t lrca, desc;
+ uint64_t lrca, id, desc;
lrca = ctx->engine[engine->id].lrc_vma->node.start +
LRC_PPHWSP_PN * PAGE_SIZE;
- desc = engine->ctx_desc_template; /* bits
0-11 */
- desc |= lrca; /* bits 12-31 */
- desc |= (lrca >> PAGE_SHIFT) << GEN8_CTX_ID_SHIFT; /* bits 32-51 */
+ id = ctx->global_id;
+
+ desc = engine->ctx_desc_template; /* bits 0-11 */
+ desc |= lrca; /* bits 12-31 */
+ desc |= id << GEN8_CTX_ID_SHIFT; /* bits 32-51 */
ctx->engine[engine->id].lrc_desc = desc;
}
@@ -335,7 +337,6 @@ uint64_t intel_lr_context_descriptor(struct intel_context
*ctx,
/**
* intel_execlists_ctx_id() - get the Execlists Context ID
* @ctx: Context to get the ID for
- * @ring: Engine to get the ID for
*
* Do not confuse with ctx->id! Unfortunately we have a name overload
* here: the old context ID we pass to userspace as a handler so that
@@ -343,15 +344,14 @@ uint64_t intel_lr_context_descriptor(struct intel_context
*ctx,
* ELSP so that the GPU can inform us of the context status via
* interrupts.
*
- * The context ID is a portion of the context descriptor, so we can
- * just extract the required part from the cached descriptor.
- *
- * Return: 20-bits globally unique context ID.
+ * Further the ID given to HW can now be relied on to be constant for
+ * the lifetime of the context, unlike previously when we used an
+ * associated logical ring context address (which could be repinned at
+ * a different address).
*/
-u32 intel_execlists_ctx_id(struct intel_context *ctx,
- struct intel_engine_cs *engine)
+u32 intel_execlists_ctx_id(struct intel_context *ctx)
{
- return intel_lr_context_descriptor(ctx, engine) >> GEN8_CTX_ID_SHIFT;
+ return ctx->global_id;
}
static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
@@ -501,7 +501,7 @@ execlists_check_remove_request(struct intel_engine_cs
*engine, u32 request_id)
if (!head_req)
return 0;
- if (unlikely(intel_execlists_ctx_id(head_req->ctx, engine) !=
request_id))
+ if (unlikely(intel_execlists_ctx_id(head_req->ctx) != request_id))
return 0;
WARN(head_req->elsp_submitted == 0, "Never submitted head request\n");
diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h
index 461f1ef..a1ff58b 100644
--- a/drivers/gpu/drm/i915/intel_lrc.h
+++ b/drivers/gpu/drm/i915/intel_lrc.h
@@ -114,8 +114,7 @@ void intel_lr_context_reset(struct drm_i915_private
*dev_priv,
uint64_t intel_lr_context_descriptor(struct intel_context *ctx,
struct intel_engine_cs *engine);
-u32 intel_execlists_ctx_id(struct intel_context *ctx,
- struct intel_engine_cs *engine);
+u32 intel_execlists_ctx_id(struct intel_context *ctx);
/* Execlists */
int intel_sanitize_enable_execlists(struct drm_device *dev, int
enable_execlists);
--
1.9.1
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