[Intel-gfx] [PATCH 3/3] drm/i915: Use writel instead of iowrite32 when programming page table entries

[Tvrtko Ursulin]

From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>

We know that the underlying area is memory and not ports so we
can use the correct accessor straight away to save on function
calls.

Especially since the gen8_set_pte already mixes writeq and
iowrite32 depending on the kernel config.

Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index c5cb04907525..6f506ab714c5 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2348,8 +2348,8 @@ static void gen8_set_pte(void __iomem *addr, gen8_pte_t 
pte)
 #ifdef writeq
        writeq(pte, addr);
 #else
-       iowrite32((u32)pte, addr);
-       iowrite32(pte >> 32, addr + 4);
+       writel((u32)pte, addr);
+       writel(pte >> 32, addr + 4);
 #endif
 }
 
@@ -2450,7 +2450,7 @@ static void gen6_ggtt_insert_entries(struct 
i915_address_space *vm,
 
        for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
                addr = sg_page_iter_dma_address(&sg_iter);
-               iowrite32(vm->pte_encode(addr, level, true, flags), 
&gtt_entries[i]);
+               writel(vm->pte_encode(addr, level, true, flags), 
&gtt_entries[i]);
                i++;
        }
 
@@ -2533,7 +2533,7 @@ static void gen6_ggtt_clear_range(struct 
i915_address_space *vm,
                                     I915_CACHE_LLC, use_scratch, 0);
 
        for (i = 0; i < num_entries; i++)
-               iowrite32(scratch_pte, &gtt_base[i]);
+               writel(scratch_pte, &gtt_base[i]);
        readl(gtt_base);
 
        assert_rpm_atomic_end(dev_priv, rpm_atomic_seq);
-- 
1.9.1

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