On ma, 2016-04-11 at 16:56 +0300, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> For a bit of extra paranoia make sure the display irqs are all
> cleared
> before we enabled them when turning on the power well. This should
> really be the case already since the power well was off which resets
> everything.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Reviewed-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 11 +++--------
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index c119610e2d57..678c6b86862e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -3306,13 +3306,6 @@ static void vlv_display_irq_postinstall(struct
> drm_i915_private *dev_priv)
> u32 iir_mask;
> enum pipe pipe;
>
> - pipestat_mask = PIPESTAT_INT_STATUS_MASK |
> - PIPE_FIFO_UNDERRUN_STATUS;
> -
> - for_each_pipe(dev_priv, pipe)
> - I915_WRITE(PIPESTAT(pipe), pipestat_mask);
> - POSTING_READ(PIPESTAT(PIPE_A));
> -
> pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
> PIPE_CRC_DONE_INTERRUPT_STATUS;
>
> @@ -3696,8 +3689,10 @@ void valleyview_enable_display_irqs(struct
> drm_i915_private *dev_priv)
>
> dev_priv->display_irqs_enabled = true;
>
> - if (intel_irqs_enabled(dev_priv))
> + if (intel_irqs_enabled(dev_priv)) {
> + vlv_display_irq_reset(dev_priv);
> vlv_display_irq_postinstall(dev_priv);
> + }
> }
>
> void valleyview_disable_display_irqs(struct drm_i915_private
> *dev_priv)
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