On Fri, Apr 08, 2016 at 05:06:04PM +0300, Ander Conselvan de Oliveira wrote:
> The function chv_data_lane_soft_reset() uses the lane count to decide
> which lanes to set/reset. However, the HDMI code never sets lane count,
> since it always uses the four lanes of the phy. Note that before commit
> a8f327fb8464 ("drm/i915: Clean up CHV lane soft reset programming"), all
> lanes were reset, regardless of lane count, so this patch restores that
> behavior.
>
> Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Cc: Deepak S <deepa...@linux.intel.com>
> Fixes: a8f327fb8464 ("drm/i915: Clean up CHV lane soft reset programming")
> Signed-off-by: Ander Conselvan de Oliveira
> <ander.conselvan.de.olive...@intel.com>
At some point we really should just eliminate the duplicated PHY code
by moving it to someting like intel_dpio.c, and then I suppose we should
populate lane_count for HDMI as well. But for now this is good enough.
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
>
> I noticed this while reading CHV code, so this is only compiled tested. I
> don't know if this could cause real issues.
>
> Ander
>
> ---
> drivers/gpu/drm/i915/intel_hdmi.c | 30 +++++++++++++-----------------
> 1 file changed, 13 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
> b/drivers/gpu/drm/i915/intel_hdmi.c
> index b199ede..5410d1a 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -1670,14 +1670,12 @@ static void chv_data_lane_soft_reset(struct
> intel_encoder *encoder,
> val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
>
> - if (crtc->config->lane_count > 2) {
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> - if (reset)
> - val &= ~(DPIO_PCS_TX_LANE2_RESET |
> DPIO_PCS_TX_LANE1_RESET);
> - else
> - val |= DPIO_PCS_TX_LANE2_RESET |
> DPIO_PCS_TX_LANE1_RESET;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
> - }
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
> + if (reset)
> + val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
> + else
> + val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
>
> val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
> val |= CHV_PCS_REQ_SOFTRESET_EN;
> @@ -1687,15 +1685,13 @@ static void chv_data_lane_soft_reset(struct
> intel_encoder *encoder,
> val |= DPIO_PCS_CLK_SOFT_RESET;
> vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
>
> - if (crtc->config->lane_count > 2) {
> - val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> - val |= CHV_PCS_REQ_SOFTRESET_EN;
> - if (reset)
> - val &= ~DPIO_PCS_CLK_SOFT_RESET;
> - else
> - val |= DPIO_PCS_CLK_SOFT_RESET;
> - vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> - }
> + val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
> + val |= CHV_PCS_REQ_SOFTRESET_EN;
> + if (reset)
> + val &= ~DPIO_PCS_CLK_SOFT_RESET;
> + else
> + val |= DPIO_PCS_CLK_SOFT_RESET;
> + vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
> }
>
> static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
> --
> 2.4.11
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
