On Fri, Apr 08, 2016 at 02:54:03PM +0300, Mika Kuoppala wrote: > For gen9 onwards, eDRAM is a true memory side cache. So > there is no need to program idi has mask as it is for eLLC > only. > > Signed-off-by: Mika Kuoppala <mika.kuopp...@intel.com> > --- > drivers/gpu/drm/i915/i915_gem.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 5a65a7663b88..71db5ca04483 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4841,7 +4841,7 @@ i915_gem_init_hw(struct drm_device *dev) > /* Double layer security blanket, see i915_gem_init() */ > intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); > > - if (dev_priv->ellc_size) > + if (dev_priv->ellc_size && INTEL_INFO(dev)->gen < 9)
INTEL_GEN(dev_priv) < 9 -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
