Starting from gen8 it's possible to use PIPE_CONTROL writing qword
instead of dword, let's add new *-qword-write tests to check coherency
of qword writes.
Signed-off-by: Michał Winiarski <michal.winiar...@intel.com>
---
tests/gem_pipe_control_store_loop.c | 49 ++++++++++++++++++++++++++++---------
1 file changed, 38 insertions(+), 11 deletions(-)
diff --git a/tests/gem_pipe_control_store_loop.c
b/tests/gem_pipe_control_store_loop.c
index a155ad1..c2cd292 100644
--- a/tests/gem_pipe_control_store_loop.c
+++ b/tests/gem_pipe_control_store_loop.c
@@ -26,7 +26,7 @@
*/
/*
- * Testcase: (TLB-)Coherency of pipe_control QW writes
+ * Testcase: (TLB-)Coherency of pipe_control writes
*
* Writes a counter-value into an always newly allocated target bo (by
disabling
* buffer reuse). Decently trashes on tlb inconsistencies, too.
@@ -43,7 +43,7 @@
#include "drm.h"
#include "intel_bufmgr.h"
-IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control QW writes.");
+IGT_TEST_DESCRIPTION("Test (TLB-)Coherency of pipe_control writes.");
static drm_intel_bufmgr *bufmgr;
struct intel_batchbuffer *batch;
@@ -60,13 +60,23 @@ uint32_t devid;
#define PIPE_CONTROL_CS_STALL (1<<20)
#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
+#define PIPE_CONTROL_STATE_BUFFER_REUSED (1 << 0)
+#define PIPE_CONTROL_STATE_QWORD_WRITE (1 << 1)
+#define PIPE_CONTROL_STATE_ALL_FLAGS (PIPE_CONTROL_STATE_BUFFER_REUSED | \
+ PIPE_CONTROL_STATE_QWORD_WRITE)
+
/* Like the store dword test, but we create new command buffers each time */
static void
-store_pipe_control_loop(bool preuse_buffer)
+store_pipe_control_loop(uint32_t flags)
{
int i, val = 0;
uint32_t *buf;
drm_intel_bo *target_bo;
+ bool preuse_buffer = flags & PIPE_CONTROL_STATE_BUFFER_REUSED;
+ bool qword_write = flags & PIPE_CONTROL_STATE_QWORD_WRITE;
+
+ if (qword_write)
+ igt_require(intel_gen(devid) >= 8);
for (i = 0; i < SLOW_QUICK(0x10000, 4); i++) {
/* we want to check tlb consistency of the pipe_control target,
@@ -97,7 +107,17 @@ store_pipe_control_loop(bool preuse_buffer)
/* gem_storedw_batches_loop.c is a bit overenthusiastic with
* creating new batchbuffers - with buffer reuse disabled, the
* support code will do that for us. */
- if (batch->gen >= 8) {
+ if (qword_write) {
+ BEGIN_BATCH(5, 1);
+ OUT_BATCH(GFX_OP_PIPE_CONTROL + 2);
+ OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
+ OUT_RELOC_FENCED(target_bo,
+ I915_GEM_DOMAIN_INSTRUCTION,
I915_GEM_DOMAIN_INSTRUCTION,
+ PIPE_CONTROL_GLOBAL_GTT);
+ OUT_BATCH(val); /* write data */
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+ } else if (batch->gen >= 8) {
BEGIN_BATCH(4, 1);
OUT_BATCH(GFX_OP_PIPE_CONTROL + 1);
OUT_BATCH(PIPE_CONTROL_WRITE_IMMEDIATE);
@@ -106,7 +126,6 @@ store_pipe_control_loop(bool preuse_buffer)
PIPE_CONTROL_GLOBAL_GTT);
OUT_BATCH(val); /* write data */
ADVANCE_BATCH();
-
} else if (batch->gen >= 6) {
/* work-around hw issue, see
intel_emit_post_sync_nonzero_flush
* in mesa sources. */
@@ -144,7 +163,11 @@ store_pipe_control_loop(bool preuse_buffer)
drm_intel_bo_map(target_bo, 1);
buf = target_bo->virtual;
- igt_assert(buf[0] == val);
+ if (qword_write)
+ /* We're always writing 0 to high dword */
+ igt_assert(((uint64_t*)buf)[0] == val);
+ else
+ igt_assert(buf[0] == val);
drm_intel_bo_unmap(target_bo);
/* Make doublesure that this buffer won't get reused. */
@@ -178,11 +201,15 @@ igt_main
igt_assert(batch);
}
- igt_subtest("fresh-buffer")
- store_pipe_control_loop(false);
-
- igt_subtest("reused-buffer")
- store_pipe_control_loop(true);
+ for (uint32_t flags = 0; flags < PIPE_CONTROL_STATE_ALL_FLAGS + 1;
flags++) {
+ igt_subtest_f("%sbuffer%s",
+ flags & PIPE_CONTROL_STATE_BUFFER_REUSED ?
+ "reused-" : "fresh-",
+ flags & PIPE_CONTROL_STATE_QWORD_WRITE ?
+ "-qword-write" : "") {
+ store_pipe_control_loop(flags);
+ }
+ }
igt_fixture {
intel_batchbuffer_free(batch);
--
2.7.1
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