On Mon, Mar 14, 2016 at 07:24:56PM +0100, Michał Winiarski wrote: > On gen8+ size of PIPE_CONTROL with Post Sync Operation should be 6 dwords.
5 or 6 depending on the size of the write. > Cc: Chris Wilson <ch...@chris-wilson.co.uk> > Signed-off-by: Michał Winiarski <michal.winiar...@intel.com> > --- > drivers/gpu/drm/i915/intel_lrc.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_lrc.c > b/drivers/gpu/drm/i915/intel_lrc.c > index 6fcbf6b..8fabca5 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -1933,7 +1933,7 @@ static int gen8_emit_request_render(struct > drm_i915_gem_request *request) > * need a prior CS_STALL, which is emitted by the flush > * following the batch. > */ > - intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(5)); > + intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); > intel_logical_ring_emit(ringbuf, > (PIPE_CONTROL_GLOBAL_GTT_IVB | > PIPE_CONTROL_CS_STALL | > @@ -1941,6 +1941,7 @@ static int gen8_emit_request_render(struct > drm_i915_gem_request *request) > intel_logical_ring_emit(ringbuf, hws_seqno_address(request->ring)); > intel_logical_ring_emit(ringbuf, 0); > intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); > + intel_logical_ring_emit(ringbuf, 0); > intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); Qword alignment forgotten anyway. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
