Op 08-03-16 om 16:46 schreef Ander Conselvan de Oliveira: > Include DPLL0 in the managed dplls for SKL/KBL. While it has to be kept > enabled because of it driving CDCLK, it is better to special case that > inside the DPLL code than in the higher level. > > v2: Use INTEL_DPLL_ALWAYS_ON flag. (Ander) > > v3: Remove extremely paranoid WARN_ONs. (Maarten) > Handle DPLL0 in skylake_get_ddi_pll() properly. (Ander) > > Signed-off-by: Ander Conselvan de Oliveira > <ander.conselvan.de.olive...@intel.com> > --- > drivers/gpu/drm/i915/intel_ddi.c | 21 ------ > drivers/gpu/drm/i915/intel_display.c | 12 +--- > drivers/gpu/drm/i915/intel_dp.c | 52 +------------- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 124 > ++++++++++++++++++++++++++-------- > drivers/gpu/drm/i915/intel_dpll_mgr.h | 7 +- > 5 files changed, 105 insertions(+), 111 deletions(-) Excellent, glad you managed to test it. :) > @@ -1176,6 +1221,19 @@ skl_get_dpll(struct intel_crtc *crtc, struct > intel_crtc_state *crtc_state, > case 270000: > ctrl1 |= > DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); > break; > + /* eDP 1.4 rates */ > + case 162000: > + ctrl1 |= > DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0); > + break; > + /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 > which > + results in CDCLK change. Need to handle the change of CDCLK by > + disabling pipes and re-enabling them */ > + case 108000: > + ctrl1 |= > DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0); > + break; > + case 216000: > + ctrl1 |= > DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0); > + break; > } > > cfgcr1 = cfgcr2 = 0; > Seems there's already a patch to address this on the mailing list, so for 12 and 13:
Reviewed-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com> _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx
