On 15/01/16 10:20, Chris Wilson wrote:
Throughout the code base, we use u32 for offsets into the global GTT. If
we ever see any hardware with a larger GGTT, then we run the real risk
of silent corruption. So test for our assumption up front so that we
have a nice reminder should the time come when it fails.
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrj...@linux.intel.com>
Cc: Daniel Vetter <dan...@ffwll.ch>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2e460b369e82..0d910638972c 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3143,6 +3143,13 @@ int i915_gem_gtt_init(struct drm_device *dev)
if (ret)
return ret;
+ if ((gtt->base.total - 1) >> 32) {
+ DRM_ERROR("We never expected a Global GTT with more than 32bits of
address space! Found %lldM!\n",
+ gtt->base.total >> 20);
+ gtt->base.total = 1ull << 32;
+ gtt->mappable_end = min(gtt->mappable_end, gtt->base.total);
Assuming Mika's comment on 'struct i915_address_space' is correct:
...
u64 start; /* Start offset always 0 for dri2 */
...
otherwise this calculation would need to be adjusted.
+
/* GMADR is the PCI mmio aperture into the global GTT. */
DRM_INFO("Memory usable by graphics device = %lluM\n",
gtt->base.total >> 20);
LGTM.
Reviewed-by: Dave Gordon <david.s.gor...@intel.com>
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