Since we do the l3-remap on context switch, and proceed to do a context
switch immediately after manually doing the l3-remap, we can remove the
redundant manual call.

Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_drv.h         |  1 -
 drivers/gpu/drm/i915/i915_gem.c         | 35 +--------------------------------
 drivers/gpu/drm/i915/i915_gem_context.c | 30 +++++++++++++++++++++++++++-
 3 files changed, 30 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f5f457920944..7dc3eed71eb3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2827,7 +2827,6 @@ bool i915_gem_clflush_object(struct drm_i915_gem_object 
*obj, bool force);
 int __must_check i915_gem_init(struct drm_device *dev);
 int i915_gem_init_rings(struct drm_device *dev);
 int __must_check i915_gem_init_hw(struct drm_device *dev);
-int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
 void i915_gem_init_swizzling(struct drm_device *dev);
 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 int __must_check i915_gpu_idle(struct drm_device *dev);
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 989222eb107b..379913221ab1 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -3951,34 +3951,6 @@ err:
        return ret;
 }
 
-int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice)
-{
-       struct drm_i915_private *dev_priv = req->i915;
-       u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
-       int i, ret;
-
-       if (!HAS_L3_DPF(dev_priv) || !remap_info)
-               return 0;
-
-       ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
-       if (ret)
-               return ret;
-
-       /*
-        * Note: We do not worry about the concurrent register cacheline hang
-        * here because no other code should access these registers other than
-        * at initialization time.
-        */
-       for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) {
-               intel_ring_emit(req->ring, MI_LOAD_REGISTER_IMM(1));
-               intel_ring_emit_reg(req->ring, GEN7_L3LOG(slice, i));
-               intel_ring_emit(req->ring, remap_info[i]);
-       }
-       intel_ring_advance(req->ring);
-
-       return ret;
-}
-
 void i915_gem_init_swizzling(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4083,7 +4055,7 @@ i915_gem_init_hw(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_engine_cs *ring;
-       int ret, i, j;
+       int ret, i;
 
        if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt())
                return -EIO;
@@ -4158,11 +4130,6 @@ i915_gem_init_hw(struct drm_device *dev)
                        goto out;
                }
 
-               if (ring->id == RCS) {
-                       for (j = 0; j < NUM_L3_SLICES(dev); j++)
-                               i915_gem_l3_remap(req, j);
-               }
-
                ret = i915_ppgtt_init_ring(req);
                if (ret && ret != -EIO) {
                        DRM_ERROR("PPGTT enable ring #%d failed %d\n", i, ret);
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c 
b/drivers/gpu/drm/i915/i915_gem_context.c
index e0ecfdfb0c8c..15e2e2abd72d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -665,6 +665,34 @@ needs_pd_load_post(struct intel_engine_cs *ring, struct 
intel_context *to,
        return false;
 }
 
+static int remap_l3(struct drm_i915_gem_request *req, int slice)
+{
+       struct drm_i915_private *dev_priv = req->i915;
+       u32 *remap_info = dev_priv->l3_parity.remap_info[slice];
+       int i, ret;
+
+       if (!HAS_L3_DPF(dev_priv) || !remap_info)
+               return 0;
+
+       ret = intel_ring_begin(req, GEN7_L3LOG_SIZE / 4 * 3);
+       if (ret)
+               return ret;
+
+       /*
+        * Note: We do not worry about the concurrent register cacheline hang
+        * here because no other code should access these registers other than
+        * at initialization time.
+        */
+       for (i = 0; i < GEN7_L3LOG_SIZE / 4; i++) {
+               intel_ring_emit(req->ring, MI_LOAD_REGISTER_IMM(1));
+               intel_ring_emit_reg(req->ring, GEN7_L3LOG(slice, i));
+               intel_ring_emit(req->ring, remap_info[i]);
+       }
+       intel_ring_advance(req->ring);
+
+       return 0;
+}
+
 static int do_switch(struct drm_i915_gem_request *req)
 {
        struct intel_context *to = req->ctx;
@@ -764,7 +792,7 @@ static int do_switch(struct drm_i915_gem_request *req)
                if (!(to->remap_slice & (1<<i)))
                        continue;
 
-               ret = i915_gem_l3_remap(req, i);
+               ret = remap_l3(req, i);
                /* If it failed, try again next round */
                if (ret)
                        DRM_DEBUG_DRIVER("L3 remapping failed\n");
-- 
2.7.0.rc3

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