On Thu, Dec 17, 2015 at 05:39:39PM +0200, Ville Syrjälä wrote:
> On Thu, Dec 17, 2015 at 05:14:54PM +0200, Mika Kuoppala wrote:
> > Since commit 940aece471bd ("drm/i915/vlv: Valleyview support
> > for forcewake Individual power wells.") we have only taken
> > media engine forcewake correctly on reads, but only taken render
> > engine forcewake on media engine writes and omitted the media
> > domain.
> >
> > This asymmetry might have caused unstable behaviour on
> > media ring access.
> >
> > Fix is to take media engine forcewake symmetrically to writes.
>
> We don't take any forcewake on writes pre-gen8. That's what the
> wake FIFO is for.
On the other hand, if something magically starts working, I think we can
conclude that our FIFO handling or the FIFO is broken. One or the other.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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