Getting guc load status does hardware access so it needs
to have pm ref.

Signed-off-by: Mika Kuoppala <mika.kuopp...@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c 
b/drivers/gpu/drm/i915/i915_debugfs.c
index 3e0e30d..5770307 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2417,6 +2417,8 @@ static int i915_guc_load_status_info(struct seq_file *m, 
void *data)
        seq_printf(m, "\tRSA: offset is %d; size = %d\n",
                guc_fw->rsa_offset, guc_fw->rsa_size);
 
+       intel_runtime_pm_get(dev_priv);
+
        tmp = I915_READ(GUC_STATUS);
 
        seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
@@ -2430,6 +2432,8 @@ static int i915_guc_load_status_info(struct seq_file *m, 
void *data)
        for (i = 0; i < 16; i++)
                seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
 
+       intel_runtime_pm_put(dev_priv);
+
        return 0;
 }
 
-- 
2.5.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reply via email to