Hi Ville: Thanks for the answer! :) Learned a lot.
I think the following scenario should be typical for a general PCI devices(perhaps a dedicated video card). How do other PCI devices handle this kinds of WC MMIO writes without GFX_FLSH_CNT? Only support UC mapping?
Thanks, Zhi. On 11/19/15 18:35, Ville Syrjälä wrote:
On Thu, Nov 19, 2015 at 06:20:23PM +0800, Zhi Wang wrote:Hi Gurus: I'm curious about the register GFX_FLSH_CNT(0x101008) in i915_gem_gtt.c. Does these register exist in recently generations? After digging into b-spec, it looks only BXT and CHV has this register. Does the desktop platform also have this register which needs to be written after updating GGTT MMIOs? BTW: Looks windows driver haven't used this MMIO... So whose behavior is the right behavior?As I understand it that register flushes the CPU GTT TLBs, and we need to do it because of the WC mapping we have for the GTT PTEs. If we used UC mapping we wouldn't need it since there's supposedly an automagic TLB flush that happens on PTE writes. BSpec is bad at finding some registers via bxml. Using dtsearch and looking for both 0x<offset> and <offset>h is the method I use to track such things down.
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