On ma, 2015-11-09 at 16:48 +0100, Patrik Jakobsson wrote:
> We never make use of the distinction between 2 vs 4 lanes so combine
> them into a per port domain instead. This saves us a few bits in the
> power domain mask. Change suggested by Ville.
>
> Signed-off-by: Patrik Jakobsson <patrik.jakobs...@linux.intel.com>
Reviewed-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 28 +++++--------
> drivers/gpu/drm/i915/i915_drv.h | 14 +++----
> drivers/gpu/drm/i915/intel_display.c | 10 ++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 71 ++++++++++++-----------
> ----------
> 4 files changed, 45 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 40ec895..2fad0a9 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2706,24 +2706,16 @@ static const char *power_domain_str(enum
> intel_display_power_domain domain)
> return "TRANSCODER_C";
> case POWER_DOMAIN_TRANSCODER_EDP:
> return "TRANSCODER_EDP";
> - case POWER_DOMAIN_PORT_DDI_A_2_LANES:
> - return "PORT_DDI_A_2_LANES";
> - case POWER_DOMAIN_PORT_DDI_A_4_LANES:
> - return "PORT_DDI_A_4_LANES";
> - case POWER_DOMAIN_PORT_DDI_B_2_LANES:
> - return "PORT_DDI_B_2_LANES";
> - case POWER_DOMAIN_PORT_DDI_B_4_LANES:
> - return "PORT_DDI_B_4_LANES";
> - case POWER_DOMAIN_PORT_DDI_C_2_LANES:
> - return "PORT_DDI_C_2_LANES";
> - case POWER_DOMAIN_PORT_DDI_C_4_LANES:
> - return "PORT_DDI_C_4_LANES";
> - case POWER_DOMAIN_PORT_DDI_D_2_LANES:
> - return "PORT_DDI_D_2_LANES";
> - case POWER_DOMAIN_PORT_DDI_D_4_LANES:
> - return "PORT_DDI_D_4_LANES";
> - case POWER_DOMAIN_PORT_DDI_E_2_LANES:
> - return "PORT_DDI_E_2_LANES";
> + case POWER_DOMAIN_PORT_DDI_A_LANES:
> + return "PORT_DDI_A_LANES";
> + case POWER_DOMAIN_PORT_DDI_B_LANES:
> + return "PORT_DDI_B_LANES";
> + case POWER_DOMAIN_PORT_DDI_C_LANES:
> + return "PORT_DDI_C_LANES";
> + case POWER_DOMAIN_PORT_DDI_D_LANES:
> + return "PORT_DDI_D_LANES";
> + case POWER_DOMAIN_PORT_DDI_E_LANES:
> + return "PORT_DDI_E_LANES";
> case POWER_DOMAIN_PORT_DSI:
> return "PORT_DSI";
> case POWER_DOMAIN_PORT_CRT:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h
> b/drivers/gpu/drm/i915/i915_drv.h
> index cef0588..fff7f63 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -180,15 +180,11 @@ enum intel_display_power_domain {
> POWER_DOMAIN_TRANSCODER_B,
> POWER_DOMAIN_TRANSCODER_C,
> POWER_DOMAIN_TRANSCODER_EDP,
> - POWER_DOMAIN_PORT_DDI_A_2_LANES,
> - POWER_DOMAIN_PORT_DDI_A_4_LANES,
> - POWER_DOMAIN_PORT_DDI_B_2_LANES,
> - POWER_DOMAIN_PORT_DDI_B_4_LANES,
> - POWER_DOMAIN_PORT_DDI_C_2_LANES,
> - POWER_DOMAIN_PORT_DDI_C_4_LANES,
> - POWER_DOMAIN_PORT_DDI_D_2_LANES,
> - POWER_DOMAIN_PORT_DDI_D_4_LANES,
> - POWER_DOMAIN_PORT_DDI_E_2_LANES,
> + POWER_DOMAIN_PORT_DDI_A_LANES,
> + POWER_DOMAIN_PORT_DDI_B_LANES,
> + POWER_DOMAIN_PORT_DDI_C_LANES,
> + POWER_DOMAIN_PORT_DDI_D_LANES,
> + POWER_DOMAIN_PORT_DDI_E_LANES,
> POWER_DOMAIN_PORT_DSI,
> POWER_DOMAIN_PORT_CRT,
> POWER_DOMAIN_PORT_OTHER,
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index c2578d9..649ac34 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5128,15 +5128,15 @@ static enum intel_display_power_domain
> port_to_power_domain(enum port port)
> {
> switch (port) {
> case PORT_A:
> - return POWER_DOMAIN_PORT_DDI_A_4_LANES;
> + return POWER_DOMAIN_PORT_DDI_A_LANES;
> case PORT_B:
> - return POWER_DOMAIN_PORT_DDI_B_4_LANES;
> + return POWER_DOMAIN_PORT_DDI_B_LANES;
> case PORT_C:
> - return POWER_DOMAIN_PORT_DDI_C_4_LANES;
> + return POWER_DOMAIN_PORT_DDI_C_LANES;
> case PORT_D:
> - return POWER_DOMAIN_PORT_DDI_D_4_LANES;
> + return POWER_DOMAIN_PORT_DDI_D_LANES;
> case PORT_E:
> - return POWER_DOMAIN_PORT_DDI_E_2_LANES;
> + return POWER_DOMAIN_PORT_DDI_E_LANES;
> default:
> WARN_ON_ONCE(1);
> return POWER_DOMAIN_PORT_OTHER;
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index c9cb94d..fc206bb 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -286,13 +286,10 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_TRANSCODER_C) | \
> BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> BIT(POWER_DOMAIN_AUX_B) | \
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_AUX_D) | \
> @@ -300,21 +297,17 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_VGA) | \
> BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_E_2_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS ( \
> (POWER_DOMAIN_MASK & ~( \
> @@ -329,10 +322,8 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_TRANSCODER_C) | \
> BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT(POWER_DOMAIN_AUX_B) | \
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_AUDIO) | \
> @@ -344,8 +335,7 @@ static void hsw_set_power_well(struct
> drm_i915_private *dev_priv,
> BIT(POWER_DOMAIN_PIPE_A) | \
> BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
> BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> BIT(POWER_DOMAIN_AUX_A) | \
> BIT(POWER_DOMAIN_PLLS) | \
> BIT(POWER_DOMAIN_INIT))
> @@ -1420,14 +1410,10 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
> BIT(POWER_DOMAIN_PIPE_A) | \
> BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
> - BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT(POWER_DOMAIN_PORT_CRT) | \
> BIT(POWER_DOMAIN_PLLS) | \
> BIT(POWER_DOMAIN_AUX_A) | \
> @@ -1451,49 +1437,42 @@ void intel_display_power_put(struct
> drm_i915_private *dev_priv,
> #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
>
> #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT(POWER_DOMAIN_PORT_CRT) | \
> BIT(POWER_DOMAIN_AUX_B) | \
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> BIT(POWER_DOMAIN_AUX_B) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> BIT(POWER_DOMAIN_AUX_B) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> BIT(POWER_DOMAIN_AUX_B) | \
> BIT(POWER_DOMAIN_AUX_C) | \
> BIT(POWER_DOMAIN_INIT))
>
> #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
> + BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> BIT(POWER_DOMAIN_AUX_D) | \
> BIT(POWER_DOMAIN_INIT))
>
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