With Fastboot by default we don't necessarily do a
full modeset enabling the primary plane.
So IPS enable call that was in that path wasn't being
called anymore.
So, let's relly on post atomic modeset path
and on ips_ready to enabled IPS when we judge necessary.
Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 14 +++++---------
drivers/gpu/drm/i915/intel_drv.h | 1 +
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index e5c4056..b2c5c55 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4607,14 +4607,6 @@ intel_post_enable_primary(struct drm_crtc *crtc)
intel_wait_for_vblank(dev, pipe);
/*
- * FIXME IPS should be fine as long as one plane is
- * enabled, but in practice it seems to have problems
- * when going from primary only to sprite only and vice
- * versa.
- */
- intel_ips_enable(intel_crtc);
-
- /*
* Gen2 reports pipe underruns whenever all planes are disabled.
* So don't enable underrun reporting before at least some planes
* are enabled.
@@ -4700,6 +4692,9 @@ static void intel_post_plane_update(struct intel_crtc
*crtc)
if (atomic->update_fbc)
intel_fbc_update(dev_priv);
+ if (atomic->enable_ips)
+ intel_ips_enable(crtc);
+
if (atomic->post_enable_primary)
intel_post_enable_primary(&crtc->base);
@@ -11578,7 +11573,8 @@ int intel_plane_atomic_calc_changes(struct
drm_crtc_state *crtc_state,
intel_crtc->atomic.disable_fbc = true;
}
-
+ if (visible && intel_crtc->config->ips_ready)
+ intel_crtc->atomic.enable_ips = true;
/*
* FBC does not work on some platforms for rotated
* planes, so disable it when rotation is not 0 and
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index cc08566..92010f7 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -538,6 +538,7 @@ struct intel_crtc_atomic_commit {
unsigned fb_bits;
bool wait_vblank;
bool update_fbc;
+ bool enable_ips;
bool post_enable_primary;
unsigned update_sprite_watermarks;
};
--
2.4.3
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
