On 11/02/2015 05:25 PM, Shobhit Kumar wrote:
The cdclock sanitization patch reviewed and merged at -
http://patchwork.freedesktop.org/patch/msgid/1445344992-14658-1-git-send-email-shobhit.ku...@intel.com
made the assumptions that DPLL should not be enabled when pre-os does not
enable display and if it does then verify that the cdclock is corectly
programmed as well. The BIOS was actually enabling DPLL as well while not
following BSPEC sequence and writing cdclk register directly. I was working
with BIOS team to correct this and found that due to a WA needed where audio
codec will not be enumerated in OS if BIOS did not program the audio verbs
which needed PG2 and DPLL enabling. More discussion revealed the following
logic -
1. BIOS puts max cdclk for the platform in CDCLK_CTL. VBIOS/GOP reads that
value and then programs cdclk to desired value.
2. It also then sets SWF18 to indicate to the OS that it has enabled display.
Used for fastmodeset actually in windows.
3. It also sets SWF06 with this max cdclock(from what bios programmed in
CDCLK_CTL) for OS to know.
This patch uses point 2 above while sanitizing the cdclk. We can also update
our logic for deciding max cdclock based on SWF06 if pre-os enables else
directly from CDCLK_CTL (no pre-os display). That is not part of this patch.
One open that comes up now is that with the sanitize implementation,
cdclock on SKL is at max 675 MHz when pre-os does not enable display.
Given that we do not have dynamic cdclk support yet, this will burn more
power in general on lower resolution. Most of the resolutions can be
supported on SKL with 337.5 MHz cdclk including 4k@30. IIRC, Ville you
were doing something on dynamic cdclk. Is there a plan on supporting that.
Regards
Shobhit
Shobhit Kumar (1):
drm/i915/skl: While sanitizing cdclock check the SWF18 as well
drivers/gpu/drm/i915/i915_reg.h | 3 +++
drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
2 files changed, 11 insertions(+)
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