On ti, 2015-10-27 at 14:47 +0200, Mika Kuoppala wrote:
> We check these to determine firmware loading status. Include
> them to help to debug causes of firmware loading fails.
>
> v2: Move all CSR specific registers to i915_reg.h (Ville)
> v3: Rebase
>
> Signed-off-by: Mika Kuoppala <mika.kuopp...@intel.com>
Reviewed-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 7 ++++++-
> drivers/gpu/drm/i915/i915_reg.h | 10 ++++++++++
> drivers/gpu/drm/i915/intel_csr.c | 13 -------------
> 3 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
> b/drivers/gpu/drm/i915/i915_debugfs.c
> index 7a61599..44b8c326 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2801,7 +2801,7 @@ static int i915_dmc_info(struct seq_file *m, void
> *unused)
> seq_printf(m, "path: %s\n", csr->fw_path);
>
> if (!csr->dmc_payload)
> - return 0;
> + goto out;
>
> seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
> CSR_VERSION_MINOR(csr->version));
> @@ -2816,6 +2816,11 @@ static int i915_dmc_info(struct seq_file *m, void
> *unused)
> I915_READ(BXT_CSR_DC3_DC5_COUNT));
> }
>
> +out:
> + seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
> + seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
> + seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c563ead..72bbed2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -5697,6 +5697,16 @@ enum skl_disp_power_wells {
> #define GAMMA_MODE_MODE_SPLIT (3 << 0)
>
> /* DMC/CSR */
> +#define CSR_PROGRAM(i) (0x80000 + (i) * 4)
> +#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
> +#define CSR_HTP_ADDR_SKL 0x00500034
> +#define CSR_SSP_BASE 0x8F074
> +#define CSR_HTP_SKL 0x8F004
> +#define CSR_LAST_WRITE 0x8F034
> +#define CSR_LAST_WRITE_VALUE 0xc003b400
> +/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
> +#define CSR_MMIO_START_RANGE 0x80000
> +#define CSR_MMIO_END_RANGE 0x8FFFF
> #define SKL_CSR_DC3_DC5_COUNT 0x80030
> #define SKL_CSR_DC5_DC6_COUNT 0x8002C
> #define BXT_CSR_DC3_DC5_COUNT 0x80038
> diff --git a/drivers/gpu/drm/i915/intel_csr.c
> b/drivers/gpu/drm/i915/intel_csr.c
> index 701c685..bd305da 100644
> --- a/drivers/gpu/drm/i915/intel_csr.c
> +++ b/drivers/gpu/drm/i915/intel_csr.c
> @@ -50,21 +50,8 @@ MODULE_FIRMWARE(I915_CSR_BXT);
> #define SKL_REQUIRED_FW_MAJOR 1
> #define SKL_REQUIRED_FW_MINOR 23
>
> -/*
> -* SKL CSR registers for DC5 and DC6
> -*/
> -#define CSR_PROGRAM(i) (0x80000 + (i) * 4)
> -#define CSR_SSP_BASE_ADDR_GEN9 0x00002FC0
> -#define CSR_HTP_ADDR_SKL 0x00500034
> -#define CSR_SSP_BASE 0x8F074
> -#define CSR_HTP_SKL 0x8F004
> -#define CSR_LAST_WRITE 0x8F034
> -#define CSR_LAST_WRITE_VALUE 0xc003b400
> -/* MMIO address range for CSR program (0x80000 - 0x82FFF) */
> #define CSR_MAX_FW_SIZE 0x2FFF
> #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
> -#define CSR_MMIO_START_RANGE 0x80000
> -#define CSR_MMIO_END_RANGE 0x8FFFF
>
> struct intel_css_header {
> /* 0x09 for DMC */
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