On Thu, 22 Oct 2015, Daniel Vetter <dan...@ffwll.ch> wrote:
> On Thu, Oct 22, 2015 at 01:56:34PM +0200, Maarten Lankhorst wrote:
>> I'm getting unclaimed register writes when checking the WM registers
>> after the crtc is disabled. So I would imagine those are guarded by
>> the crtc power well. Fix this by not reading out wm state when the
>> power well is off.
>>
>> Signed-off-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92181
>> Cc: sta...@vger.kernel.org
>
> Reviewed-by: Daniel Vetter <daniel.vet...@ffwll.ch>
>
> Jani, one for you.
This one pushed to drm-intel-fixes, thanks for the patch and review.
I dropped cc: stable because this will still make it to v4.3, and we're
not backporting SKL fixes beyond that.
BR,
Jani.
> -Daniel
>
>> ---
>> drivers/gpu/drm/i915/intel_pm.c | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index 4c1c1bb96a9e..fbc10331055e 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -2833,7 +2833,12 @@ void skl_ddb_get_hw_state(struct drm_i915_private
>> *dev_priv,
>> int plane;
>> u32 val;
>>
>> + memset(ddb, 0, sizeof(*ddb));
>> +
>> for_each_pipe(dev_priv, pipe) {
>> + if (!intel_display_power_is_enabled(dev_priv,
>> POWER_DOMAIN_PIPE(pipe)))
>> + continue;
>> +
>> for_each_plane(dev_priv, pipe, plane) {
>> val = I915_READ(PLANE_BUF_CFG(pipe, plane));
>> skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
>> --
>> 2.1.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Jani Nikula, Intel Open Source Technology Center
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