On Wed, 14 Oct 2015 15:51:39 -0700
Kevin Strasser <kevin.stras...@linux.intel.com> wrote:

> On HSW the crc differs between black and disabled primary planes, causing an
> assert to fail in the kms_universal_plane test. It seems that gamma correction
> and color space conversion are causing the black primary plane case to result 
> in
> a brighter color than the disabled primary plane case.
> 
> Keep gamma and CSC bits enabled for plane disable path on HSW.
> 
> v2: Avoid use of RMW
>     Keep path unchanged for non-HSW users
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89331
> Testcase: igt/kms_universal_plane/universal-plane-pipe-A-functional
> Signed-off-by: Kevin Strasser <kevin.stras...@linux.intel.com>

Reviewed-by: Bob Paauwe <bob.j.paa...@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_display.c | 16 ++++++++++------
>  1 file changed, 10 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c 
> b/drivers/gpu/drm/i915/intel_display.c
> index d37b7a1..4a04e8b 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2798,8 +2798,17 @@ static void ironlake_update_primary_plane(struct 
> drm_crtc *crtc,
>       u32 reg = DSPCNTR(plane);
>       int pixel_size;
>  
> +     dspcntr = DISPPLANE_GAMMA_ENABLE;
> +
> +     if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> +             dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> +
>       if (!visible || !fb) {
> -             I915_WRITE(reg, 0);
> +             if (IS_HASWELL(dev)) {
> +                     I915_WRITE(reg, dspcntr);
> +             } else {
> +                     I915_WRITE(reg, 0);
> +             }
>               I915_WRITE(DSPSURF(plane), 0);
>               POSTING_READ(reg);
>               return;
> @@ -2811,13 +2820,8 @@ static void ironlake_update_primary_plane(struct 
> drm_crtc *crtc,
>  
>       pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
>  
> -     dspcntr = DISPPLANE_GAMMA_ENABLE;
> -
>       dspcntr |= DISPLAY_PLANE_ENABLE;
>  
> -     if (IS_HASWELL(dev) || IS_BROADWELL(dev))
> -             dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
> -
>       switch (fb->pixel_format) {
>       case DRM_FORMAT_C8:
>               dspcntr |= DISPPLANE_8BPP;



-- 
--
Bob Paauwe                  
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp.  Folsom, CA
(916) 356-6193    

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