On Mon, 28 Sep 2015, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> v2: Keep some MISSING_CASE() stuff (Jani)
> s/-1/-PIPE_B/ in the register macro
> Fix typo in patch subject
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 102
> ++++++++++++++++++++-------------------
> drivers/gpu/drm/i915/intel_dp.c | 23 +++------
> drivers/gpu/drm/i915/intel_psr.c | 5 +-
> 3 files changed, 63 insertions(+), 67 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 2c518a0..7723ed3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3068,11 +3068,7 @@ enum skl_disp_power_wells {
> #define EDP_PSR_IDLE_FRAME_SHIFT 0
>
> #define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
> -#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) +
> 0x14)
> -#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) +
> 0x18)
> -#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) +
> 0x1c)
> -#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) +
> 0x20)
> -#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) +
> 0x24)
> +#define EDP_PSR_AUX_DATA(dev, i) (EDP_PSR_BASE(dev) + 0x14 + (i)
> * 4) /* 5 registers */
>
> #define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) +
> 0x40)
> #define EDP_PSR_STATUS_STATE_MASK (7<<29)
> @@ -4188,33 +4184,36 @@ enum skl_disp_power_wells {
> * is 20 bytes in each direction, hence the 5 fixed
> * data registers
> */
> -#define DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset +
> 0x64010)
> -#define DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
> -#define DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
> -#define DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
> -#define DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
> -#define DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
> -
> -#define DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset +
> 0x64110)
> -#define DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
> -#define DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
> -#define DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
> -#define DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
> -#define DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
> -
> -#define DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset +
> 0x64210)
> -#define DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
> -#define DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
> -#define DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
> -#define DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
> -#define DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
> -
> -#define DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset +
> 0x64310)
> -#define DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
> -#define DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
> -#define DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
> -#define DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
> -#define DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
> +#define _DPA_AUX_CH_CTL (dev_priv->info.display_mmio_offset +
> 0x64010)
> +#define _DPA_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64014)
> +#define _DPA_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64018)
> +#define _DPA_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6401c)
> +#define _DPA_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64020)
> +#define _DPA_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64024)
> +
> +#define _DPB_AUX_CH_CTL (dev_priv->info.display_mmio_offset +
> 0x64110)
> +#define _DPB_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64114)
> +#define _DPB_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64118)
> +#define _DPB_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6411c)
> +#define _DPB_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64120)
> +#define _DPB_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64124)
> +
> +#define _DPC_AUX_CH_CTL (dev_priv->info.display_mmio_offset +
> 0x64210)
> +#define _DPC_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64214)
> +#define _DPC_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64218)
> +#define _DPC_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6421c)
> +#define _DPC_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64220)
> +#define _DPC_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64224)
> +
> +#define _DPD_AUX_CH_CTL (dev_priv->info.display_mmio_offset +
> 0x64310)
> +#define _DPD_AUX_CH_DATA1 (dev_priv->info.display_mmio_offset + 0x64314)
> +#define _DPD_AUX_CH_DATA2 (dev_priv->info.display_mmio_offset + 0x64318)
> +#define _DPD_AUX_CH_DATA3 (dev_priv->info.display_mmio_offset + 0x6431c)
> +#define _DPD_AUX_CH_DATA4 (dev_priv->info.display_mmio_offset + 0x64320)
> +#define _DPD_AUX_CH_DATA5 (dev_priv->info.display_mmio_offset + 0x64324)
> +
> +#define DP_AUX_CH_CTL(port) _PORT(port, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
> +#define DP_AUX_CH_DATA(port, i) (_PORT(port, _DPA_AUX_CH_DATA1,
> _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>
> #define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
> #define DP_AUX_CH_CTL_DONE (1 << 30)
> @@ -6549,28 +6548,31 @@ enum skl_disp_power_wells {
> #define BXT_PP_OFF_DELAYS(n) _PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
>
> #define PCH_DP_B 0xe4100
> -#define PCH_DPB_AUX_CH_CTL 0xe4110
> -#define PCH_DPB_AUX_CH_DATA1 0xe4114
> -#define PCH_DPB_AUX_CH_DATA2 0xe4118
> -#define PCH_DPB_AUX_CH_DATA3 0xe411c
> -#define PCH_DPB_AUX_CH_DATA4 0xe4120
> -#define PCH_DPB_AUX_CH_DATA5 0xe4124
> +#define _PCH_DPB_AUX_CH_CTL 0xe4110
> +#define _PCH_DPB_AUX_CH_DATA1 0xe4114
> +#define _PCH_DPB_AUX_CH_DATA2 0xe4118
> +#define _PCH_DPB_AUX_CH_DATA3 0xe411c
> +#define _PCH_DPB_AUX_CH_DATA4 0xe4120
> +#define _PCH_DPB_AUX_CH_DATA5 0xe4124
>
> #define PCH_DP_C 0xe4200
> -#define PCH_DPC_AUX_CH_CTL 0xe4210
> -#define PCH_DPC_AUX_CH_DATA1 0xe4214
> -#define PCH_DPC_AUX_CH_DATA2 0xe4218
> -#define PCH_DPC_AUX_CH_DATA3 0xe421c
> -#define PCH_DPC_AUX_CH_DATA4 0xe4220
> -#define PCH_DPC_AUX_CH_DATA5 0xe4224
> +#define _PCH_DPC_AUX_CH_CTL 0xe4210
> +#define _PCH_DPC_AUX_CH_DATA1 0xe4214
> +#define _PCH_DPC_AUX_CH_DATA2 0xe4218
> +#define _PCH_DPC_AUX_CH_DATA3 0xe421c
> +#define _PCH_DPC_AUX_CH_DATA4 0xe4220
> +#define _PCH_DPC_AUX_CH_DATA5 0xe4224
>
> #define PCH_DP_D 0xe4300
> -#define PCH_DPD_AUX_CH_CTL 0xe4310
> -#define PCH_DPD_AUX_CH_DATA1 0xe4314
> -#define PCH_DPD_AUX_CH_DATA2 0xe4318
> -#define PCH_DPD_AUX_CH_DATA3 0xe431c
> -#define PCH_DPD_AUX_CH_DATA4 0xe4320
> -#define PCH_DPD_AUX_CH_DATA5 0xe4324
> +#define _PCH_DPD_AUX_CH_CTL 0xe4310
> +#define _PCH_DPD_AUX_CH_DATA1 0xe4314
> +#define _PCH_DPD_AUX_CH_DATA2 0xe4318
> +#define _PCH_DPD_AUX_CH_DATA3 0xe431c
> +#define _PCH_DPD_AUX_CH_DATA4 0xe4320
> +#define _PCH_DPD_AUX_CH_DATA5 0xe4324
> +
> +#define PCH_DP_AUX_CH_CTL(port) _PORT((port) - PORT_B,
> _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL)
> +#define PCH_DP_AUX_CH_DATA(port, i) (_PORT((port) - PORT_B,
> _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
>
> /* CPT */
> #define PORT_TRANS_A_SEL_CPT 0
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 1180289..d252feb 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -751,7 +751,7 @@ static uint32_t i9xx_get_aux_send_ctl(struct intel_dp
> *intel_dp,
> else
> precharge = 5;
>
> - if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
> + if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg ==
> DP_AUX_CH_CTL(PORT_A))
> timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
> else
> timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
> @@ -1014,14 +1014,12 @@ static uint32_t g4x_aux_ctl_reg(struct
> drm_i915_private *dev_priv,
> {
> switch (port) {
> case PORT_B:
> - return DPB_AUX_CH_CTL;
> case PORT_C:
> - return DPC_AUX_CH_CTL;
> case PORT_D:
> - return DPD_AUX_CH_CTL;
> + return DP_AUX_CH_CTL(port);
> default:
> MISSING_CASE(port);
> - return DPB_AUX_CH_CTL;
> + return DP_AUX_CH_CTL(PORT_A);
Changes default from port B to A.
Otherwise,
Reviewed-by: Jani Nikula <jani.nik...@intel.com>
> }
> }
>
> @@ -1030,16 +1028,14 @@ static uint32_t ilk_aux_ctl_reg(struct
> drm_i915_private *dev_priv,
> {
> switch (port) {
> case PORT_A:
> - return DPA_AUX_CH_CTL;
> + return DP_AUX_CH_CTL(port);
> case PORT_B:
> - return PCH_DPB_AUX_CH_CTL;
> case PORT_C:
> - return PCH_DPC_AUX_CH_CTL;
> case PORT_D:
> - return PCH_DPD_AUX_CH_CTL;
> + return PCH_DP_AUX_CH_CTL(port);
> default:
> MISSING_CASE(port);
> - return DPA_AUX_CH_CTL;
> + return DP_AUX_CH_CTL(PORT_A);
> }
> }
>
> @@ -1075,16 +1071,13 @@ static uint32_t skl_aux_ctl_reg(struct
> drm_i915_private *dev_priv,
>
> switch (port) {
> case PORT_A:
> - return DPA_AUX_CH_CTL;
> case PORT_B:
> - return DPB_AUX_CH_CTL;
> case PORT_C:
> - return DPC_AUX_CH_CTL;
> case PORT_D:
> - return DPD_AUX_CH_CTL;
> + return DP_AUX_CH_CTL(port);
> default:
> MISSING_CASE(port);
> - return DPA_AUX_CH_CTL;
> + return DP_AUX_CH_CTL(PORT_A);
> }
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 213581c..ff66718 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -166,6 +166,7 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> [3] = 1 - 1,
> [4] = DP_SET_POWER_D0,
> };
> + enum port port = dig_port->port;
> int i;
>
> BUILD_BUG_ON(sizeof(aux_msg) > 20);
> @@ -182,9 +183,9 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
> DP_AUX_FRAME_SYNC_ENABLE);
>
> aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
> - DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
> + DP_AUX_CH_DATA(port, 0) : EDP_PSR_AUX_DATA(dev, 0);
> aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
> - DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
> + DP_AUX_CH_CTL(port) : EDP_PSR_AUX_CTL(dev);
>
> /* Setup AUX registers */
> for (i = 0; i < sizeof(aux_msg); i += 4)
> --
> 2.4.6
>
--
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
