On 09/18/2015 10:03 AM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> Parametrize the SWF registers. This also fixes the register offsets,
> which were mostly garbage in the old defines.
>
> Also save/restore only as many SWF registers that each platform has.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 28 +++++++++++------------
> drivers/gpu/drm/i915/i915_suspend.c | 45
> ++++++++++++++++++++++++++++---------
> 3 files changed, 50 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3bf8a9b..3e35e08 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1041,7 +1041,7 @@ struct i915_suspend_saved_registers {
> u32 saveMI_ARB_STATE;
> u32 saveSWF0[16];
> u32 saveSWF1[16];
> - u32 saveSWF2[3];
> + u32 saveSWF3[3];
> uint64_t saveFENCE[I915_MAX_NUM_FENCES];
> u32 savePCH_PORT_HOTPLUG;
> u16 saveGCDGMBUS;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 0cc41e4b..57b9469 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4941,20 +4941,20 @@ enum skl_disp_power_wells {
> #define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
> #define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
>
> -/* VBIOS flags */
> -#define SWF00 (dev_priv->info.display_mmio_offset +
> 0x71410)
> -#define SWF01 (dev_priv->info.display_mmio_offset +
> 0x71414)
> -#define SWF02 (dev_priv->info.display_mmio_offset +
> 0x71418)
> -#define SWF03 (dev_priv->info.display_mmio_offset +
> 0x7141c)
> -#define SWF04 (dev_priv->info.display_mmio_offset +
> 0x71420)
> -#define SWF05 (dev_priv->info.display_mmio_offset +
> 0x71424)
> -#define SWF06 (dev_priv->info.display_mmio_offset +
> 0x71428)
> -#define SWF10 (dev_priv->info.display_mmio_offset +
> 0x70410)
> -#define SWF11 (dev_priv->info.display_mmio_offset +
> 0x70414)
> -#define SWF14 (dev_priv->info.display_mmio_offset +
> 0x71420)
> -#define SWF30 (dev_priv->info.display_mmio_offset +
> 0x72414)
> -#define SWF31 (dev_priv->info.display_mmio_offset +
> 0x72418)
> -#define SWF32 (dev_priv->info.display_mmio_offset +
> 0x7241c)
> +/*
> + * VBIOS flags
> + * gen2:
> + * [00:06] alm,mgm
> + * [10:16] all
> + * [30:32] alm,mgm
> + * gen3+:
> + * [00:0f] all
> + * [10:1f] all
> + * [30:32] all
> + */
> +#define SWF0(i) (dev_priv->info.display_mmio_offset + 0x70410 + (i) * 4)
> +#define SWF1(i) (dev_priv->info.display_mmio_offset + 0x71410 + (i) * 4)
> +#define SWF3(i) (dev_priv->info.display_mmio_offset + 0x72414 + (i) * 4)
>
> /* Pipe B */
> #define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c
> b/drivers/gpu/drm/i915/i915_suspend.c
> index 1ccac61..2d91821 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -122,12 +122,24 @@ int i915_save_state(struct drm_device *dev)
> dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
>
> /* Scratch space */
> - for (i = 0; i < 16; i++) {
> - dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
> - dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
> + if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
> + for (i = 0; i < 7; i++) {
> + dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
> + dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> + }
> + for (i = 0; i < 3; i++)
> + dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
> + } else if (IS_GEN2(dev_priv)) {
> + for (i = 0; i < 7; i++)
> + dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> + } else if (HAS_GMCH_DISPLAY(dev_priv)) {
> + for (i = 0; i < 16; i++) {
> + dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
> + dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
> + }
> + for (i = 0; i < 3; i++)
> + dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
> }
> - for (i = 0; i < 3; i++)
> - dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
>
> mutex_unlock(&dev->struct_mutex);
>
> @@ -156,12 +168,25 @@ int i915_restore_state(struct drm_device *dev)
> /* Memory arbitration state */
> I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE |
> 0xffff0000);
>
> - for (i = 0; i < 16; i++) {
> - I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
> - I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
> + /* Scratch space */
> + if (IS_GEN2(dev_priv) && IS_MOBILE(dev_priv)) {
> + for (i = 0; i < 7; i++) {
> + I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
> + I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> + }
> + for (i = 0; i < 3; i++)
> + I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
> + } else if (IS_GEN2(dev_priv)) {
> + for (i = 0; i < 7; i++)
> + I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> + } else if (HAS_GMCH_DISPLAY(dev_priv)) {
> + for (i = 0; i < 16; i++) {
> + I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
> + I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
> + }
> + for (i = 0; i < 3; i++)
> + I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
> }
> - for (i = 0; i < 3; i++)
> - I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
>
> mutex_unlock(&dev->struct_mutex);
>
>
I think these were added speculatively in the first place. Maybe we'd
see a bug on 8xx without these saved & restored, but I wonder if we'd
see anything else?
Reviewed-by: Jesse Barnes <jbar...@virtuousgeek.org>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
