On Tue, Sep 22, 2015 at 01:48:44PM -0700, yu....@intel.com wrote:
> From: Alex Dai <yu....@intel.com>
>
> GuC expects two bits for Render and Media domain separately when
> driver sends data via host2guc SAMPLE_FORCEWAKE. Bit 0 is for
> Render and bit 1 is for Media domain.
>
> v1: Add parameters definition to avoid magic value
>
> Signed-off-by: Alex Dai <yu....@intel.com>
Reviewed-by: Tom O'Rourke <Tom.O'rou...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_guc_submission.c | 6 ++++--
> drivers/gpu/drm/i915/intel_guc_fwif.h | 3 +++
> 2 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c
> b/drivers/gpu/drm/i915/i915_guc_submission.c
> index 38b6ef4..7dbc108 100644
> --- a/drivers/gpu/drm/i915/i915_guc_submission.c
> +++ b/drivers/gpu/drm/i915/i915_guc_submission.c
> @@ -158,9 +158,11 @@ static int host2guc_sample_forcewake(struct intel_guc
> *guc,
> u32 data[2];
>
> data[0] = HOST2GUC_ACTION_SAMPLE_FORCEWAKE;
> - data[1] = (intel_enable_rc6(dev_priv->dev)) ? 1 : 0;
> + /* bit 0 and 1 are for Render and Media domain separately */
> + data[1] = intel_enable_rc6(dev_priv->dev) ?
> + GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA : 0;
>
> - return host2guc_action(guc, data, 2);
> + return host2guc_action(guc, data, ARRAY_SIZE(data));
> }
>
> /*
> diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h
> b/drivers/gpu/drm/i915/intel_guc_fwif.h
> index f6d0aa4..ecea053 100644
> --- a/drivers/gpu/drm/i915/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
> @@ -260,6 +260,9 @@ struct guc_context_desc {
> #define GUC_POWER_D2 3
> #define GUC_POWER_D3 4
>
> +#define GUC_FORCEWAKE_RENDER (1 << 0)
> +#define GUC_FORCEWAKE_MEDIA (1 << 1)
> +
> /* This Action will be programmed in C180 - SOFT_SCRATCH_O_REG */
> enum host2guc_action {
> HOST2GUC_ACTION_DEFAULT = 0x0,
> --
> 1.9.1
>
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