Disable Turbo on steppings prior to B0 on BXT due to hangs seen during GT CPD 
exit.

v3: Explicitly clear the Turbo control register (Akash)

Change-Id: I50c5c03f59f5ba092db19e17234951d89db42c6c
Signed-off-by: Akash Goel <akash.g...@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kam...@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 62de97e..b679e8e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4479,6 +4479,10 @@ static void gen6_set_rps(struct drm_device *dev, u8 val)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
 
+       /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
+       if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0))
+               return;
+
        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
        WARN_ON(val > dev_priv->rps.max_freq);
        WARN_ON(val < dev_priv->rps.min_freq);
@@ -4799,6 +4803,22 @@ static void gen9_enable_rps(struct drm_device *dev)
 
        gen6_init_rps_frequencies(dev);
 
+       /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
+       if (IS_BROXTON(dev) && (INTEL_REVID(dev) < BXT_REVID_B0)) {
+               /*
+                * BIOS could leave the Hw Turbo enabled, so need to explicitly
+                * clear out the Control register just to avoid inconsitency
+                * with debugfs interface, which will show  Turbo as enabled
+                * only, which is not expected by the User after adding the
+                * WaGsvDisableTurbo. Apart from this there is no problem even
+                * if the Turbo is left enabled in the Control register, as the
+                * Up/Down interrupts would remain masked.
+                */
+               I915_WRITE(GEN6_RP_CONTROL, 0);
+               intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
+               return;
+       }
+
        /* Program defaults and thresholds for RPS*/
        I915_WRITE(GEN6_RC_VIDEO_FREQ,
                GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
-- 
1.9.1

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