From: Ville Syrjälä <ville.syrj...@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++----
drivers/gpu/drm/i915/intel_dp.c | 17 ++++++++---------
2 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ddfcd68..134b075 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6537,10 +6537,10 @@ enum skl_disp_power_wells {
#define _BXT_PP_ON_DELAYS2 0xc7308
#define _BXT_PP_OFF_DELAYS2 0xc730c
-#define BXT_PP_STATUS(n) ((!n) ? PCH_PP_STATUS : _BXT_PP_STATUS2)
-#define BXT_PP_CONTROL(n) ((!n) ? PCH_PP_CONTROL : _BXT_PP_CONTROL2)
-#define BXT_PP_ON_DELAYS(n) ((!n) ? PCH_PP_ON_DELAYS : _BXT_PP_ON_DELAYS2)
-#define BXT_PP_OFF_DELAYS(n) ((!n) ? PCH_PP_OFF_DELAYS : _BXT_PP_OFF_DELAYS2)
+#define BXT_PP_STATUS(n) _PIPE(n, PCH_PP_STATUS, _BXT_PP_STATUS2)
+#define BXT_PP_CONTROL(n) _PIPE(n, PCH_PP_CONTROL, _BXT_PP_CONTROL2)
+#define BXT_PP_ON_DELAYS(n) _PIPE(n, PCH_PP_ON_DELAYS, _BXT_PP_ON_DELAYS2)
+#define BXT_PP_OFF_DELAYS(n) _PIPE(n, PCH_PP_OFF_DELAYS, _BXT_PP_OFF_DELAYS2)
#define PCH_DP_B 0xe4100
#define PCH_DPB_AUX_CH_CTL 0xe4110
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index a687250..7e64555 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -546,7 +546,7 @@ static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dp_to_dev(intel_dp);
if (IS_BROXTON(dev))
- return BXT_PP_CONTROL(0);
+ return BXT_PP_CONTROL(1);
else if (HAS_PCH_SPLIT(dev))
return PCH_PP_CONTROL;
else
@@ -558,7 +558,7 @@ static u32 _pp_stat_reg(struct intel_dp *intel_dp)
struct drm_device *dev = intel_dp_to_dev(intel_dp);
if (IS_BROXTON(dev))
- return BXT_PP_STATUS(0);
+ return BXT_PP_STATUS(1);
else if (HAS_PCH_SPLIT(dev))
return PCH_PP_STATUS;
else
@@ -5318,9 +5318,9 @@ intel_dp_init_panel_power_sequencer(struct drm_device
*dev,
* Correct Register for Broxton need to be identified
* using VBT. hardcoding for now
*/
- pp_ctrl_reg = BXT_PP_CONTROL(0);
- pp_on_reg = BXT_PP_ON_DELAYS(0);
- pp_off_reg = BXT_PP_OFF_DELAYS(0);
+ pp_ctrl_reg = BXT_PP_CONTROL(1);
+ pp_on_reg = BXT_PP_ON_DELAYS(1);
+ pp_off_reg = BXT_PP_OFF_DELAYS(1);
} else if (HAS_PCH_SPLIT(dev)) {
pp_ctrl_reg = PCH_PP_CONTROL;
pp_on_reg = PCH_PP_ON_DELAYS;
@@ -5438,10 +5438,9 @@ intel_dp_init_panel_power_sequencer_registers(struct
drm_device *dev,
* Correct Register for Broxton need to be identified
* using VBT. hardcoding for now
*/
- pp_ctrl_reg = BXT_PP_CONTROL(0);
- pp_on_reg = BXT_PP_ON_DELAYS(0);
- pp_off_reg = BXT_PP_OFF_DELAYS(0);
-
+ pp_ctrl_reg = BXT_PP_CONTROL(1);
+ pp_on_reg = BXT_PP_ON_DELAYS(1);
+ pp_off_reg = BXT_PP_OFF_DELAYS(1);
} else if (HAS_PCH_SPLIT(dev)) {
pp_on_reg = PCH_PP_ON_DELAYS;
pp_off_reg = PCH_PP_OFF_DELAYS;
--
2.4.6
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
