On ma, 2015-06-22 at 14:37 +0100, Damien Lespiau wrote: > On Wed, Jun 17, 2015 at 02:00:54PM +0300, Imre Deak wrote: > > For GEN9 the target cdclk frequency is needed during the modeset state check > > phase too, so factor out this functionality. > > > > Signed-off-by: Imre Deak <imre.d...@intel.com> > > I believe the "proper" way to do it is to put what you called the target > CDCLK in the atomic state and use that here. Maarten has a patch to do > that towards the end of his atomic series.
Yes, I was also thinking of using a pre-calculated value, but that looked like a bigger work. I haven't seen Maarten's patch but that looks like the way to go (Daniel also pointed to this on IRC). So I can rebase this once Maarten's patchset lands. --Imre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
