From: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
There is no need to "recompute" it every time since it is guaranteed
to be static for the lifetime of a frame buffer being assigned to a
plane for display purposes.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 17 +++++++++++------
drivers/gpu/drm/i915/intel_drv.h | 6 ++++++
drivers/gpu/drm/i915/intel_sprite.c | 8 ++------
3 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 95a2375..182477f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2334,6 +2334,7 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
struct drm_device *dev = fb->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
+ struct intel_plane_state *intel_plane_state;
struct i915_ggtt_view view;
u32 alignment;
int ret;
@@ -2398,6 +2399,12 @@ intel_pin_and_fence_fb_obj(struct drm_plane *plane,
if (ret)
goto err_interruptible;
+ if (plane_state) {
+ intel_plane_state = to_intel_plane_state(plane_state);
+ intel_plane_state->disp_addr =
+ intel_plane_obj_offset(intel_plane_state, obj);
+ }
+
/* Install a fence for tiled scan-out. Pre-i965 always needs a
* fence, whereas 965+ only requires a fence if using
* framebuffer compression. For simplicity, we always install
@@ -3034,7 +3041,6 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
u32 tile_height, plane_offset, plane_size;
unsigned int rotation;
int x_offset, y_offset;
- unsigned long surf_addr;
struct intel_crtc_state *crtc_state = intel_crtc->config;
struct intel_plane_state *plane_state;
int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
@@ -3064,7 +3070,6 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
obj = intel_fb_obj(fb);
stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
fb->pixel_format);
- surf_addr = intel_plane_obj_offset(plane_state, obj);
/*
* FIXME: intel_plane_state->src, dst aren't set when transitional
@@ -3124,7 +3129,7 @@ static void skylake_update_primary_plane(struct drm_crtc
*crtc,
I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
}
- I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
+ I915_WRITE(PLANE_SURF(pipe, 0), plane_state->disp_addr);
POSTING_READ(PLANE_SURF(pipe, 0));
}
@@ -11558,8 +11563,8 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
if (ret)
goto cleanup_pending;
- work->gtt_offset =
intel_plane_obj_offset(to_intel_plane_state(primary->state),
- obj) +
intel_crtc->dspaddr_offset;
+ work->gtt_offset = to_intel_plane_state(primary->state)->disp_addr +
+ intel_crtc->dspaddr_offset;
if (mmio_flip) {
ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
@@ -13990,7 +13995,7 @@ intel_commit_cursor_plane(struct drm_plane *plane,
if (!obj)
addr = 0;
else if (!INTEL_INFO(dev)->cursor_needs_physical)
- addr = i915_gem_obj_ggtt_offset(obj);
+ addr = state->disp_addr;
else
addr = obj->phys_handle->busaddr;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 5599f43..5e18a42 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -274,6 +274,12 @@ struct intel_plane_state {
* update_scaler_users.
*/
int scaler_id;
+
+ /*
+ * Cached display address at the time framebuffer is prepared for use
+ * on a plane.
+ */
+ unsigned long disp_addr;
};
struct intel_initial_plane_config {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c
b/drivers/gpu/drm/i915/intel_sprite.c
index f123090..fc9e797 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -177,13 +177,11 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
struct drm_device *dev = drm_plane->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_plane *intel_plane = to_intel_plane(drm_plane);
- struct drm_i915_gem_object *obj = intel_fb_obj(fb);
const int pipe = intel_plane->pipe;
const int plane = intel_plane->plane + 1;
u32 plane_ctl, stride_div, stride;
int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
const struct drm_intel_sprite_colorkey *key = &intel_plane->ckey;
- unsigned long surf_addr;
u32 tile_height, plane_offset, plane_size;
unsigned int rotation;
int x_offset, y_offset;
@@ -225,9 +223,6 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
else if (key->flags & I915_SET_COLORKEY_SOURCE)
plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
- surf_addr =
intel_plane_obj_offset(to_intel_plane_state(drm_plane->state),
- obj);
-
if (intel_rotation_90_or_270(rotation)) {
/* stride: Surface height in tiles */
tile_height = intel_tile_height(dev, fb->pixel_format,
@@ -268,7 +263,8 @@ skl_update_plane(struct drm_plane *drm_plane, struct
drm_crtc *crtc,
}
I915_WRITE(PLANE_CTL(pipe, plane), plane_ctl);
- I915_WRITE(PLANE_SURF(pipe, plane), surf_addr);
+ I915_WRITE(PLANE_SURF(pipe, plane),
+ to_intel_plane_state(drm_plane->state)->disp_addr);
POSTING_READ(PLANE_SURF(pipe, plane));
}
--
2.4.2
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