From: Akash Goel <akash.g...@intel.com>
Read the efficient frequency (aka RPe) value through the the mailbox
command (0x1A) from the pcode, as done on Haswell and Broadwell.
The turbo minimum frequency softlimit is not revised as per the
efficient frequency value.
Issue: VIZ-5143
Signed-off-by: Akash Goel <akash.g...@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d091fec..1d14cce2 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4314,16 +4314,20 @@ static void gen6_init_rps_frequencies(struct drm_device
*dev)
dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
- if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
+ if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
ret = sandybridge_pcode_read(dev_priv,
HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
&ddcc_status);
- if (0 == ret)
+ if (0 == ret) {
dev_priv->rps.efficient_freq =
clamp_t(u8,
((ddcc_status >> 8) & 0xff),
dev_priv->rps.min_freq,
dev_priv->rps.max_freq);
+
+ dev_priv->rps.efficient_freq *=
+ (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
+ }
}
dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
--
1.9.2
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