Use for_each_crtc_state to only touch affected crtc's.
In order to make sure that the initial power is still set
correctly we make sure modeset_update_crtc_power_domains is called
during the initial modeset.
Signed-off-by: Maarten Lankhorst <maarten.lankho...@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 3 ---
drivers/gpu/drm/i915/intel_display.c | 46 +++++++++++++++++++++++-------------
2 files changed, 29 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index d3632c56fdf7..78ef0bb53c36 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -634,9 +634,6 @@ static int i915_drm_suspend(struct drm_device *dev)
intel_display_suspend(dev);
drm_modeset_unlock_all(dev);
- /* suspending displays will unsets init power */
- intel_display_set_init_power(dev_priv, true);
-
intel_dp_mst_suspend(dev);
intel_runtime_pm_disable_interrupts(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 1936a28a57c1..64c84fb94b4d 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5188,42 +5188,50 @@ static unsigned long get_crtc_power_domains(struct
drm_crtc *crtc)
return mask;
}
-static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
+static void modeset_update_crtc_power_domains(struct drm_atomic_state *state,
+ bool power_only)
{
struct drm_device *dev = state->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
- struct intel_crtc *crtc;
+ unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }, domains;
+ struct drm_crtc_state *crtc_state;
+ struct drm_crtc *crtc;
+ int i;
/*
* First get all needed power domains, then put all unneeded, to avoid
* any unnecessary toggling of the power wells.
*/
- for_each_intel_crtc(dev, crtc) {
+ for_each_crtc_in_state(state, crtc, crtc_state, i) {
enum intel_display_power_domain domain;
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
- if (!crtc->base.state->enable)
+ if (!crtc->state->active)
continue;
- pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
+ domains = pipe_domains[pipe] = get_crtc_power_domains(crtc);
+ domains &= ~to_intel_crtc(crtc)->enabled_power_domains;
- for_each_power_domain(domain, pipe_domains[crtc->pipe])
+ for_each_power_domain(domain, domains)
intel_display_power_get(dev_priv, domain);
}
- if (dev_priv->display.modeset_global_resources)
+ if (!power_only && dev_priv->display.modeset_global_resources)
dev_priv->display.modeset_global_resources(state);
- for_each_intel_crtc(dev, crtc) {
+ for_each_crtc_in_state(state, crtc, crtc_state, i) {
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ enum pipe pipe = intel_crtc->pipe;
enum intel_display_power_domain domain;
- for_each_power_domain(domain, crtc->enabled_power_domains)
- intel_display_power_put(dev_priv, domain);
+ domains = intel_crtc->enabled_power_domains;
+ domains &= ~pipe_domains[pipe];
- crtc->enabled_power_domains = pipe_domains[crtc->pipe];
- }
+ intel_crtc->enabled_power_domains = pipe_domains[pipe];
- intel_display_set_init_power(dev_priv, false);
+ for_each_power_domain(domain, domains)
+ intel_display_power_put(dev_priv, domain);
+ }
}
void broxton_set_cdclk(struct drm_device *dev, int frequency)
@@ -12719,7 +12727,7 @@ static int __intel_set_mode(struct drm_atomic_state
*state)
/* The state has been swaped above, so state actually contains the
* old state now. */
- modeset_update_crtc_power_domains(state);
+ modeset_update_crtc_power_domains(state, false);
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
for_each_crtc_in_state(state, crtc, crtc_state, i) {
@@ -15235,14 +15243,16 @@ void intel_modeset_setup_hw_state(struct drm_device
*dev,
return;
}
+ /* swap sw/hw state */
drm_atomic_helper_swap_state(dev, state);
-
- /* swap sw/hw dpll state */
intel_atomic_duplicate_dpll_state(dev_priv, shared_dplls);
intel_shared_dpll_commit(state);
memcpy(to_intel_atomic_state(state)->shared_dpll,
shared_dplls, sizeof(*shared_dplls) * dev_priv->num_shared_dpll);
+ /* update power state to match hw state */
+ modeset_update_crtc_power_domains(state, true);
+
/* HW state is read out, now we need to sanitize this mess. */
for_each_intel_encoder(dev, encoder) {
intel_sanitize_encoder(encoder);
@@ -15310,6 +15320,8 @@ void intel_modeset_setup_hw_state(struct drm_device
*dev,
drm_atomic_state_free(state);
}
+ intel_display_set_init_power(dev_priv, false);
+
intel_modeset_check_state(dev);
}
--
2.1.0
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