Imre Deak <imre.d...@intel.com> writes:
> v2:
> - set the override disable flag too on stepping F0 (mika)
>
> Signed-off-by: Imre Deak <imre.d...@intel.com>
[PATCH pre4/4] drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on
steppings B0+
And this patch,
Reviewed-by: Mika Kuoppala <mika.kuopp...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 15 ++++++++-------
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 643fe89..2472415 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -918,6 +918,7 @@ static int gen9_init_workarounds(struct intel_engine_cs
> *ring)
> {
> struct drm_device *dev = ring->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> + uint32_t tmp;
>
> /* WaDisablePartialInstShootdown:skl,bxt */
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> @@ -973,6 +974,13 @@ static int gen9_init_workarounds(struct intel_engine_cs
> *ring)
> WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1,
> GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE);
>
> + /* WaForceContextSaveRestoreNonCoherent:skl,bxt */
> + tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
> + if ((IS_SKYLAKE(dev) && INTEL_REVID(dev) == SKL_REVID_F0) ||
> + (IS_BROXTON(dev) && INTEL_REVID(dev) >= BXT_REVID_B0))
> + tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
> + WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
> +
> return 0;
> }
>
> @@ -1049,7 +1057,6 @@ static int bxt_init_workarounds(struct intel_engine_cs
> *ring)
> {
> struct drm_device *dev = ring->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - uint32_t tmp;
>
> gen9_init_workarounds(ring);
>
> @@ -1057,12 +1064,6 @@ static int bxt_init_workarounds(struct intel_engine_cs
> *ring)
> WA_SET_BIT_MASKED(GEN8_ROW_CHICKEN,
> STALL_DOP_GATING_DISABLE);
>
> - /* WaForceContextSaveRestoreNonCoherent:bxt */
> - tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT;
> - if (INTEL_REVID(dev) >= BXT_REVID_B0)
> - tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE;
> - WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp);
> -
> return 0;
> }
>
> --
> 2.1.4
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