On Wed, May 20, 2015 at 02:45:17PM +0100, Damien Lespiau wrote:
> Right not we don't initialize the stored CDCLK on DDI platforms. Fix
> that.
>
> Signed-off-by: Damien Lespiau <damien.lesp...@intel.com>
Merged up to this patch, thanks, Daniel
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index d602db2..b57f156 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2518,8 +2518,8 @@ void intel_ddi_pll_init(struct drm_device *dev)
> else
> hsw_shared_dplls_init(dev_priv);
>
> - DRM_DEBUG_KMS("CDCLK running at %dKHz\n",
> - dev_priv->display.get_display_clock_speed(dev));
> + dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
> + DRM_DEBUG_KMS("CDCLK running at %dKHz\n", dev_priv->cdclk_freq);
>
> if (IS_SKYLAKE(dev)) {
> if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
> --
> 2.1.0
>
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--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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