The divider value to convert from CZ clock rate to ms needs a +1
adjustment on VLV just like on CHV. This matches both the spec and
the accuracy test by pm_rc6_residency.
Testcase: igt/pm_rc6_residency
Signed-off-by: Imre Deak <imre.d...@intel.com>
---
drivers/gpu/drm/i915/i915_sysfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c
b/drivers/gpu/drm/i915/i915_sysfs.c
index 2476268..aa99efc 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -76,6 +76,8 @@ static u32 calc_residency(struct drm_device *dev, const u32
reg)
/* chv counts are one less */
czcount_30ns += 1;
}
+ } else {
+ czcount_30ns += 1;
}
if (units == 0)
--
2.1.4
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