Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_irq.c | 24 ++++++++++--------------
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 47c9c02e6731..eecbbab921d9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2090,9 +2090,8 @@ static irqreturn_t ironlake_irq_handler(int irq, void
*arg)
intel_uncore_check_errors(dev);
/* disable master interrupt before clearing iir */
- de_ier = I915_READ(DEIER);
- I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
- POSTING_READ(DEIER);
+ de_ier = I915_READ_FW(DEIER);
+ I915_WRITE_FW(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
/* Disable south interrupts. We'll only write to SDEIIR once, so further
* interrupts will will be stored on its back queue, and then we'll be
@@ -2100,16 +2099,15 @@ static irqreturn_t ironlake_irq_handler(int irq, void
*arg)
* it, we'll get an interrupt if SDEIIR still has something to process
* due to its back queue). */
if (!HAS_PCH_NOP(dev)) {
- sde_ier = I915_READ(SDEIER);
- I915_WRITE(SDEIER, 0);
- POSTING_READ(SDEIER);
+ sde_ier = I915_READ_FW(SDEIER);
+ I915_WRITE_FW(SDEIER, 0);
}
/* Find, clear, then process each source of interrupt */
- gt_iir = I915_READ(GTIIR);
+ gt_iir = I915_READ_FW(GTIIR);
if (gt_iir) {
- I915_WRITE(GTIIR, gt_iir);
+ I915_WRITE_FW(GTIIR, gt_iir);
ret = IRQ_HANDLED;
if (INTEL_INFO(dev)->gen >= 6)
snb_gt_irq_handler(dev, dev_priv, gt_iir);
@@ -2136,12 +2134,10 @@ static irqreturn_t ironlake_irq_handler(int irq, void
*arg)
}
}
- I915_WRITE(DEIER, de_ier);
- POSTING_READ(DEIER);
- if (!HAS_PCH_NOP(dev)) {
- I915_WRITE(SDEIER, sde_ier);
- POSTING_READ(SDEIER);
- }
+ I915_WRITE_FW(DEIER, de_ier);
+ if (!HAS_PCH_NOP(dev))
+ I915_WRITE_FW(SDEIER, sde_ier);
+ POSTING_READ_FW(DEIER);
return ret;
}
--
2.1.4
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