Hi Experts and Gurus:
I'm learning i915 and It looks like in i915_gem_context.c: mi_set_context(),
the last intel_ring_advance(); is a lazy ring tail write. So I think the ring
buffer contains MI_SET_CONTEXT will not be submitted at this time, but in the
caller: do_switch() it will unpin the backing memory of the context GEM object.
From this time the backing memory may be swapped out? Then in the execbuffer
routines, the MI_SET_CONTEXT may save current HW state into an unexpected
location I guess?
do_switch()
-> mi_set_context()
-> intel_ring_begin()
->emit MI_SET_CONTEXT (save current HW state to "prev" context and
load engine state from "next" context, but it won't be submitted at this time)
->intel_ring_advance()
-> unpin and unreference "prev" context(from this time the "prev" context
can be swapped by shrinker I think)
Then we come into the time of real submission:
i915_gem_execbuffer_retire_commands()
-> __intel_ring_advance() (MI_SET_CONTEXT got submitted at this time, but
the "prev" context in do_switch() may be swapped out and turned into invalid?
If GPU save current engine state into "prev" context, the "prev" context should
be corrupted? When it got switch back, there should be problem I think.)
I think a solution should be:
- Changing intel_ring_advance() to __intel_ring_davnce() in mi_set_context()->
submit the MI_SET_CONTEXT ring buffer directly at this time.
- Polling CCID register until the new engine state is load into HW.
Then the "prev" context can be unpinned and unreferenced safely?
I'm just a beginner, If you can confirm this is an issue or a potential
problem, I can cook a patch. :)
Thanks,
Zhi.
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