Re: [Intel-gfx] [PATCH] drm/i915: Check lane sharing between pipes B & C using atomic state

[shuang . he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
Task id: 6080
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  276/276              276/276
ILK                                  303/303              303/303
SNB                                  304/304              304/304
IVB                 -2              330/330              328/330
BYT                                  287/287              287/287
HSW                                  361/361              361/361
BDW                                  309/309              309/309
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series 
Applied
*IVB  igt@gem_storedw_batches_loop@normal      PASS(6)      DMESG_WARN(1)PASS(1)
(dmesg patch 
applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck
 timer elapsed... blitter ring idle
*IVB  igt@gem_pwrite_pread@snooped-copy-performance      PASS(5)      
DMESG_WARN(2)
(dmesg patch 
applied)drm:i915_hangcheck_elapsed[i915]]*ERROR*Hangcheck_timer_elapsed...blitter_ring_idle@Hangcheck
 timer elapsed... blitter ring idle
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