On Thu, Jan 15, 2015 at 11:21:30AM +0000, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursu...@intel.com> > > This eliminates six needless spin lock/unlock pairs when writing out ELSP. > Apart > from tidier code main benefit is between 0.51% and 0.73% speedup on some OGL > tests under CHV (bench_OglBatch4 bench_OglDeferred respectively).
With 95% confidence t-test on n=5 > > Kindly benchmarked by Ben Widawsky. FWIW, as I mentioned on IRC, I think the reduction of the unnecessary forcewake (someone should fix the shadow register list) is probably more beneficial than removing the spin on an uncontested lock. I was tempted to try that myself, but I didn't have time or much interest since your patch accomplishes the same thing. The sucky thing, which I actually care about since I've been doing a lot of profiling, is the raw MMIO doesn't show up with our i915 trace functions. It's obtainable still, but then I get a mess of other stuff I don't want. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursu...@intel.com> > Cc: Dave Gordon <david.s.gor...@intel.com> > Cc: Daniel Vetter <daniel.vet...@ffwll.ch> > Cc: Ben Widawsky <b...@bwidawsk.net> [snip] _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
