On Mon, 08 Dec 2014, Daniel Vetter <daniel.vet...@ffwll.ch> wrote:
> After a bit of irc discussion we've concluded that it would be prudent
> to check that callers use the mask/enable paramters correctly. So add
> a WARN_ON.
>
> Spurred by Damien's bugfix which added _MASKED_FIELD.
>
> v2: We use WARN_ON(1) a lot to catch default cases in switch blocks
> which should always be extended. So this doesn't work really. Dunno
> why gcc only started complaining when I've moved the WARN out of the
> static inline helper to address a feedback from Jani.
Ah, that would be precisely because of the static inline helper. The
function parameter is never a builtin constant!
BR,
Jani.
>
> Cc: Damien Lespiau <damien.lesp...@intel.com>
> Cc: Chris Wilson <ch...@chris-wilson.co.uk>
> Cc: Jani Nikula <jani.nik...@linux.intel.com>
> Signed-off-by: Daniel Vetter <daniel.vet...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 08a5a4ba52ac..e6a1db36928e 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -183,6 +183,8 @@ static void ilk_update_gt_irq(struct drm_i915_private
> *dev_priv,
> {
> assert_spin_locked(&dev_priv->irq_lock);
>
> + WARN_ON(enabled_irq_mask & ~interrupt_mask);
> +
> if (WARN_ON(!intel_irqs_enabled(dev_priv)))
> return;
>
> @@ -229,6 +231,8 @@ static void snb_update_pm_irq(struct drm_i915_private
> *dev_priv,
> {
> uint32_t new_val;
>
> + WARN_ON(enabled_irq_mask & ~interrupt_mask);
> +
> assert_spin_locked(&dev_priv->irq_lock);
>
> new_val = dev_priv->pm_irq_mask;
> @@ -328,6 +332,8 @@ void ibx_display_interrupt_update(struct drm_i915_private
> *dev_priv,
> sdeimr &= ~interrupt_mask;
> sdeimr |= (~enabled_irq_mask & interrupt_mask);
>
> + WARN_ON(enabled_irq_mask & ~interrupt_mask);
> +
> assert_spin_locked(&dev_priv->irq_lock);
>
> if (WARN_ON(!intel_irqs_enabled(dev_priv)))
> --
> 2.1.1
>
--
Jani Nikula, Intel Open Source Technology Center
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