Hi Bob,
Thanks for the patch. Just a small comment below.
On 11/11/2014 01:09 AM, Bob Paauwe wrote:
> Use the new pipe config values to calculate the updated pll dividers.
>
> This regression was introduced in
>
> commit 0dbdf89f27b17ae1eceed6782c2917f74cbb5d59
> Author: Ander Conselvan de Oliveira <ander.conselvan.de.olive...@intel.com>
> Date: Wed Oct 29 11:32:33 2014 +0200
>
> drm/i915: Add infrastructure for choosing DPLLs before disabling crtcs
>
> and
>
> commit 00d958817dd3daaa452c221387ddaf23d1e4c06f
> Author: Ander Conselvan de Oliveira
> <ander.conselvan.de.olive...@intel.com>
> Date: Wed Oct 29 11:32:36 2014 +0200
>
> drm/i915: Covert remaining platforms to choose DPLLS before
> disabling CRTCs
>
> Signed-off-by: Bob Paauwe <bob.j.paa...@intel.com>
> CC: Ander Conselvan de Oliveira <ander.conselvan.de.olive...@intel.com>
> CC: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index ff071a7..601641d 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5730,24 +5730,24 @@ static void i9xx_update_pll_dividers(struct
> intel_crtc *crtc,
> u32 fp, fp2 = 0;
>
> if (IS_PINEVIEW(dev)) {
> - fp = pnv_dpll_compute_fp(&crtc->config.dpll);
> + fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
> if (reduced_clock)
> fp2 = pnv_dpll_compute_fp(reduced_clock);
> } else {
> - fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
> + fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
> if (reduced_clock)
> fp2 = i9xx_dpll_compute_fp(reduced_clock);
> }
>
> - crtc->config.dpll_hw_state.fp0 = fp;
> + crtc->new_config->dpll_hw_state.fp0 = fp;
>
> crtc->lowfreq_avail = false;
> if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
This needs to be changed to intel_pipe_will_have_type(), so that it
looks at the new configuration instead of the current one. With that
fixed,
Reviewed-by: Ander Conselvan de Oliveira <ander.conselvan.de.olive...@intel.com>
> reduced_clock && i915.powersave) {
> - crtc->config.dpll_hw_state.fp1 = fp2;
> + crtc->new_config->dpll_hw_state.fp1 = fp2;
> crtc->lowfreq_avail = true;
> } else {
> - crtc->config.dpll_hw_state.fp1 = fp;
> + crtc->new_config->dpll_hw_state.fp1 = fp;
> }
> }
>
>
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