On Thu, 06 Nov 2014, Rodrigo Vivi <rodrigo.v...@intel.com> wrote: > Global GTT doesn't have pat_sel[2:0] so it always point to pat_sel = 000; > So the only way to avoid screen corruptions is setting PAT 0 to Uncached. > > MOCS can still be used though. But if userspace is trusting PTE for > cache selection the safest thing to do is to let caches disabled. > > BSpec: "For GGTT, there is NO pat_sel[2:0] from the entry, > so RTL will always use the value corresponding to pat_sel = 000" > > - System agent ggtt writes (i.e. cpu gtt mmaps) already work before > this patch, i.e. the same uncached + snooping access like on gen6/7 > seems to be in effect. > - So this just fixes blitter/render access. Again it looks like it's > not just uncached access, but uncached + snooping. So we can still > hold onto all our assumptions wrt cpu clflushing on LLC machines. > > v2: Cleaner patch as suggested by Chris. > v3: Add Daniel's comment > > Reference: https://bugs.freedesktop.org/show_bug.cgi?id=85576 > Cc: Chris Wilson <ch...@chris-wilson.co.uk> > Cc: James Ausmus <james.aus...@intel.com> > Cc: Daniel Vetter <daniel.vet...@ffwll.ch> > Cc: Jani Nikula <jani.nik...@intel.com> > Cc: sta...@vger.kernel.org > Tested-by: James Ausmus <james.aus...@intel.com> > Reviewed-by: James Ausmus <james.aus...@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
Pushed this one to drm-intel-fixes as-is, thanks for the patch, review, and bikeshedding. :p BR, Jani. > --- > drivers/gpu/drm/i915/i915_gem_gtt.c | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c > b/drivers/gpu/drm/i915/i915_gem_gtt.c > index cb7adab..6d3fb3c 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -1920,6 +1920,22 @@ static void bdw_setup_private_ppat(struct > drm_i915_private *dev_priv) > GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) > | > GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3)); > > + if (!USES_PPGTT(dev_priv->dev)) > + /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry, > + * so RTL will always use the value corresponding to > + * pat_sel = 000". > + * So let's disable cache for GGTT to avoid screen corruptions. > + * MOCS still can be used though. > + * - System agent ggtt writes (i.e. cpu gtt mmaps) already work > + * before this patch, i.e. the same uncached + snooping access > + * like on gen6/7 seems to be in effect. > + * - So this just fixes blitter/render access. Again it looks > + * like it's not just uncached access, but uncached + snooping. > + * So we can still hold onto all our assumptions wrt cpu > + * clflushing on LLC machines. > + */ > + pat = GEN8_PPAT(0, GEN8_PPAT_UC); > + > /* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b > * write would work. */ > I915_WRITE(GEN8_PRIVATE_PAT, pat); > -- > 1.9.3 > -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
